4.1 Conclusion
In this thesis, a new TFT structure featuring suspended NW channels was proposed and successfully demonstrated. The device features a side-gate configuration and the formation of NW channels is realized by a simple and low cost sidewall spacer etching technique. The suspension of the NW channels is achieved by stripping off the sacrificial oxide between the NW channels and the gate nitride layer.
The fabricated devices show hysteresis phenomenon in the transfer characteristics due to the action of the suspended NW channels. The hysteresis characteristics are strongly dependent on the NW dimensions, channel length, as well as the thickness of the air gap. For the device with smaller NW’s cross sectional dimensions, better performance is obtained. This is attributed to the higher flexibility of the smaller NW channel so that a larger portion of the slimmer NW channels is connected with the gate nitride as the gate voltage is high. With a reasonable air gap thickness (25.5 nm), the devices show a large hysteresis window (2.4 V) in the transfer characteristics.
Also, a better S.S. is presented despite the higher EOT of gate dielectric. Oscillation phenomenon of S.S. due to the motion of the NW channels is also observed. A model taking into account the gradual contact procedure of suspended NW channels with gate nitride owing to the electrostatic force is proposed to explain the experimental observations.
4.2 Future Work
The development and characterization of a novel suspended-channel device have been carried out in this thesis. To improve the performance of the device, a new layout of the devices is proposed. As shown in Fig. 4-1, the new layout of the suspended NW channels devices have S/D extensions existing at the two sides and an intrinsic channel at the central part of the NW channels. With the addition of the S/D extensions, the suspended NW channels would contact the gate nitride more intimately. This scheme would allow a significant increase in the portion of the intrinsic channels in contact with the gate nitride during device operation (Fig. 4-1(b)), further lowering in the threshold voltage and S.S. is expected. Moreover, the parasitic resistance of the device can be reduced to achieve a larger current drive.
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Table 3-1Comparisons of suspended NW channel devices with different air gap thickness.
Device with 4.5 nm air gap
Device with 25.5 nm air gap
Vpi (V)
2.41 2.51
S.S. (mV/dec)
185 142
Table 3-2 Comparisons of suspended NW devices with different over etch time (with 4.5 nm air gap thickness and 0.4 μm channel length).
O.E. 17S O.E. 27S
Vpi (V)
2.8 2.58
S.S. (mV/dec)
243 216
Table 3-3 Comparisons of suspended NW devices with different over etch time (with 25.5 nm air gap thickness and 1 μm channel length).
O.E. 17S O.E. 27S
Vpi (V)
3.09 2.51
S.S. (mV/dec)
239 142
Table 3-4 Comparisons of suspended NW channel devices with different air gap thickness.
Device with 4.5 nm air gap
Device with 25.5 nm air gap
Vpi (V)
2.41 2.51
Vpo (V)0.95 0.11
pull-in S.S. (mV/dec)
185 142
pull-out S.S. (mV/dec)
299 269
Window of hysteresis (V)
1.46 2.4
Fig.1-1(a) Schematic views of basic device structure of n-channel I-MOS and the band diagrams of the ON \ OFF state. [17]
Fig.1-1(b) a) An electron arrives at the edge of the strong field region at random time τ1. b) The carrier starts impact ionization and avalanche, thereby generating more carriers. However, the multiplication process with fewer carriers is strongly fluctuating and random, until the number of carrier reaches a reasonable amount (about 50) and overcome the randomness in multiplication process. c) The multiplication process continues until the device is fully turned on. [21]
Fig. 1-1(c) In order to achieve a reliable circuit operation, failure rate less than 1ppm while the device is on is essential (which means only one failure every million operations). For conventional CMOS, the intrinsic delay of 1ppm operation is just a few picosenconds (or less than one). However, with off-state level of 1 μA/μm, I-MOS needs 10 picoseconds for a 1ppm operation. In the trade off between on/off current ratio and dynamic operation delay, I-MOS does not show advantage over conventional CMOS. [21]