In this thesis, we have shown several approaches on optimizing LPSC in physical design and their tradeoffs in previous sections. With the LPSC reordering, we can alleviate both test power and routing overhead issues on scan chain design. Since we do not constrain chaining scan cells in a specific cluster region, our approach has more freedom to choose better scan cell connection. With well defined cost function for weighted graph, we can also obtain better test power and routing cost optimization more explicitly.
In the past, scan chain reordering focused on shortening connection length, re-ducing routing congestion, making TSP algorithm more efficient, moderating scan chain timing violation, etc. These scan chain optimization approaches may alleviate impact on routing overhead or timing convergence in the design. As scan based BIST test architecture becomes more popular in modern ASICs and SoCs, scan test power problem should also be paid much attention to. From our experimental results, we can control parameter to adjust about 30% scan test power reduction ratio. While the optimizing degree in scan test power is strongly correlated with scan chain routing overhead, we can not always to have β=1.0 which has best scan test power reduction ratio but poorest routing congestion. On the other hand, scan test power reduction ratio generating by considering both power and routing
over-head may not be enough for test mode in modern circuit design since test mode may consume twice more power than normal function mode. In order to further reduce test power, we can cooperate our scan chain reordering approach with multiple scan chains architectures [13]. Since multiple scan chains architectures can shorten tran-sition shifting path, this can enormously reduce switching per scan cell. We have experimented on two scan chains architecture on benchmark s9234 and found that we can have 50% transition reduction ratio with normal wire length driven scan chain reordering and 62% transition reduction ratio in our reordering approach with β=1.0. Again, we can control scan test power reduction ratio from 50% to 62% by
adjusting β.
To further reduce test mode power, we can add low power ATPG test patterns in the design and use this technique to collaborate with our reordering approach and multiple scan chain architecture. We will focus on integrating these technique and continue discussing low power test architecture in our future work.
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自傳
許力中，1980 年 10 月 17 日生，台灣省台中市人◦ 2003 年自交通大學電子工
程系畢業，繼續進入交大電子工程研究所攻讀碩士學位，研究興趣為超大 型積體電路實體自動化設計與計算機結構，主修為數位電路設計與電腦輔 助設計◦論文題目為「低功率循序串列於細部佈局、佈局之後及繞線上最佳 化方法研究」◦