• 沒有找到結果。

6.1 Conclusion

In this thesis, we implemented an I-Frame decoder with parallelism technique and memory reduction method to achieve low memory, high throughput HEVC video decoder.

From the system point of view, first considering the memory requirement in the total video decoder, the intra predictor and deblocking filter occupy almost 83% totally and the power con-sumption occupy about 15.3% of all. Therefore, with higher resolution, the memory require-ments and power consumption would harm the hardware processing. By the proposed shared above line buffer for the deleting 1-line buffer for deblocking filter, it could save the internal memory to the 20% reduction ratio of all. Further, the prediction-based memory hierarchy for containing 1/8 frame size of internal SRAM for the deblocking filter is limited for the system point considering the external memory bandwidth and SDRAM power consumption. Compared with the [27], the hit rate could achieve better performance in the SRAM reduction factor set as 8. In Figure 5.8, the hit rate is improved about 14% in the Full-HD sequence. While the external memory bandwidth in the miss penalty is reduced about the 36.1% in the Full-HD se-quence. For accessing the external memory, the power consumes in the SDRAM would also be considered to the system. In Table 5.3, the SDRAM power could also be reduced 36% for only 3.6mW. In the proposed architecture, the I-frame decoder consists of the transform coder,

intra predictor and in-loop filter which are improved the throughput which can be enhanced to decode 8Kx4K super-high vision by using the wavefront parallel processing and the internal memories could be reduced using the shared above line buffer and the second level memory hierarchy, as a result, the proposed work could be applied to the super-high vision mulimedia application and the low power portable devices.

6.2 Future Work

In the future work, the application of the multimedia video codec could be applied to the intelligent video surveillance (IVS). The engine camera could track and record the motion of the objects and also identify the information of the objects. Moreover, as the information of the video could appeal to the viewers, the decoder must combine with the detection engine used to specify the human’s gestures and also the cloud computing is the important technique to complete this application.

Bibliography

[1] T.-M. Liu and C.-Y. Lee, “Memory-hierarchy-based power reduction for h. 264/avc video decoder,” in VLSI Design, Automation and Test, 2006 International Symposium on, 2006, pp. 1–4.

[2] C.-C. Lin, J.-W. Chen, H.-C. Chang, Y.-C. Yang, Y.-H. O. Yang, M.-C. Tsai, J.-I. Guo, and J.-S. Wang, “A 160k gates/4.5 kb sram h.264 video decoder for hdtv applications,”

Solid-State Circuits, IEEE Journal of, vol. 42, no. 1, pp. 170–182, 2007.

[3] J. Shah, K. S. Raghunandan, and K. Varghese, “Hd resolution intra prediction architec-ture for h.264 decoder,” in VLSI Design (VLSID), 2012 25th International Conference on, 2012, pp. 107–112.

[4] D. Zhou, G. He, W. Fei, Z. Chen, J. Zhou, and S. Goto, “A 4320p 60fps h.264/avc intra-frame encoder chip with 1.41gbins/s cabac,” in VLSI Circuits (VLSIC), 2012 Symposium on, 2012, pp. 154–155.

[5] Y.-C. Chao, J.-K. Lin, J.-F. Yang, and B.-D. Liu, “A high throughput and data reuse ar-chitecture for h.264/avc deblocking filter,” in Circuits and Systems, 2006. APCCAS 2006.

IEEE Asia Pacific Conference on, 2006, pp. 1260–1263.

[6] Y.-W. Huang, T.-W. Chen, B.-Y. Hsieh, T.-C. Wang, T.-H. Chang, and L.-G. Chen, “Archi-tecture design for deblocking filter in h.264/jvt/avc,” in Multimedia and Expo, 2003. ICME

’03. Proceedings. 2003 International Conference on, vol. 1, 2003, pp. I–693–6 vol.1.

[7] S.-C. Chang, W.-H. Peng, S.-H. Wang, and T. Chiang, “A platform based bus-interleaved architecture for de-blocking filter in h.264/mpeg-4 avc,” Consumer Electronics, IEEE Transactions on, vol. 51, no. 1, pp. 249–255, 2005.

[8] B. Sheng, W. Gao, and D. Wu, “An implemented architecture of deblocking filter for h.264/avc,” in Image Processing, 2004. ICIP ’04. 2004 International Conference on, vol. 1, 2004, pp. 665–668 Vol. 1.

[9] C.-C. Cheng, T.-S. Chang, and K.-B. Lee, “An in-place architecture for the deblocking filter in h.264/avc,” Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 53, no. 7, pp. 530–534, 2006.

[10] M. Sima, Y. Zhou, and W. Zhang, “An efficient architecture for adaptive deblocking filter of h.264/avc video coding,” Consumer Electronics, IEEE Transactions on, vol. 50, no. 1, pp. 292–296, 2004.

[11] T.-W. Chen, Y.-W. Huang, T.-C. Chen, Y.-H. Chen, C.-Y. Tsai, and L.-G. Chen, “Architec-ture design of h.264/avc decoder with hybrid task pipelining for high definition videos,”

in Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on, 2005, pp.

2931–2934 Vol. 3.

[12] D. Zhou, J. Zhou, X. He, J. Zhu, J. Kong, P. Liu, and S. Goto, “A 530 mpixels/s 4096x2160@60fps h.264/avc high profile video decoder chip,” Solid-State Circuits, IEEE Journal of, vol. 46, no. 4, pp. 777–788, 2011.

[13] D. Zhou, J. Zhou, J. Zhu, P. Liu, and S. Goto, “A 2gpixel/s h.264/avc hp/mvc video de-coder chip for super hi-vision and 3dtv/ftv applications,” in Solid-State Circuits Confer-ence Digest of Technical Papers (ISSCC), 2012 IEEE International, 2012, pp. 224–226.

[14] T.-A. Lin, S.-Z. Wang, T.-M. Liu, and C.-Y. Lee, “An h.264/avc decoder with 4 times;4-block level pipeline,” in Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on, 2005, pp. 1810–1813 Vol. 2.

[15] D. Zhou, Z. You, J. Zhu, J. Kong, Y. Hong, X. Chen, X. He, C. Xu, H. Zhang, J. Zhou, N. Deng, P. Liu, and S. Goto, “A 1080p@60fps multi-standard video decoder chip de-signed for power and cost efficiency in a system perspective,” in VLSI Circuits, 2009 Symposium on, 2009, pp. 262–263.

[16] T.-D. Chuang, P.-K. Tsung, P.-C. Lin, L.-M. Chang, T.-C. Ma, Y.-H. Chen, and L.-G.

Chen, “A 59.5mw scalable/multi-view video decoder chip for quad/3d full hdtv and video streaming applications,” in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International, 2010, pp. 330–331.

[17] C.-T. Huang, M. Tikekar, C. Juvekar, V. Sze, and A. Chandrakasan, “A 249mpixel/s hevc video-decoder chip for quad full hd applications,” in Solid-State Circuits Conference Di-gest of Technical Papers (ISSCC), 2013 IEEE International, 2013, pp. 162–163.

[18] K.-H. Chen, J.-I. Guo, K.-C. Chao, J.-S. Wang, and Y.-S. Chu, “A high-performance low power direct 2-d transform coding ip design for mpeg-4 avc/h.264 with a switching power suppression technique,” in VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT).

2005 IEEE VLSI-TSA International Symposium on, 2005, pp. 291–294.

[19] C.-T. Lin, Y.-C. Yu, and L.-D. Van, “Cost-effective triple-mode reconfigurable pipeline fft/ifft/2-d dct processor,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 16, no. 8, pp. 1058–1071, 2008.

[20] C.-C. Sun, P. Donner, and J. Gotze, “Low-complexity multi-purpose ip core for quantized discrete cosine and integer transform,” in Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on, 2009, pp. 3014–3017.

[21] Y.-F. Lai and Y.-K. Lai, “Design and implementation of reconfigurable idct architecture for multi-standard video decoders,” in SoC Design Conference (ISOCC), 2010 International, 2010, pp. 107–110.

[22] Y.-H. Chen and T.-Y. Chang, “A high performance video transform engine by using space-time scheduling strategy,” Very Large Scale Integration (VLSI) Systems, IEEE Transac-tions on, vol. 20, no. 4, pp. 655–664, 2012.

[23] M. Horowitz, A. Joch, F. Kossentini, and A. Hallapuro, “H.264/avc baseline profile de-coder complexity analysis,” Circuits and Systems for Video Technology, IEEE Transac-tions on, vol. 13, no. 7, pp. 704–716, 2003.

[24] N. Kanopoulos, N. Vasanthavada, and R. L. Baker, “Design of an image edge detection filter using the sobel operator,” Solid-State Circuits, IEEE Journal of, vol. 23, no. 2, pp.

358–367, 1988.

[25] T.-M. Liu, W.-P. Lee, T.-A. Lin, and C.-Y. Lee, “A memory-efficient deblocking filter for h.264/avc video coding,” in Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on, 2005, pp. 2140–2143 Vol. 3.

[26] M. Nadeem, S. Wong, G. Kuzmanov, A. Shabbir, M. Nadeem, and F. Anjam, “Low-power, high-throughput deblocking filter for h.264/avc,” in System on Chip (SoC), 2010 International Symposium on, 2010, pp. 93–98.

[27] T.-M. Liu, T.-A. Lin, S.-Z. Wang, W.-P. Lee, J.-Y. Yang, K.-C. Hou, and C.-Y. Lee, “A 125 956;w , fully scalable mpeg-2 and h.264/avc video decoder for mobile applications,”

Solid-State Circuits, IEEE Journal of, vol. 42, no. 1, pp. 161–169, 2007.

相關文件