5.1 Conclusion
In this thesis, a novel decoder architecture for non-binary QC-LDPC codes with improved EMS decoding algorithm was proposed. Using 90-nm CMOS process, a (2,4)-regular non-binary QC-LDPC decoder over GF(26) is implemented. To the best of our knowledge, this is the first chip of non-binary LDPC decoder using EMS decoding algorithm and high order finite field (≥ GF(26)).
Compared with state-of-the-art, our design has 5 advantages. First, we enhance the through-out in CES and VES, which are the main computation units in the decoder. In the implementa-tion of nm = 8, it can reach over 100 Mbps throughout with only 655 K gate counts (564 K gate count only for decoder). Second, because of the code property that variable node degree is 2, we can reduce half storage elements for edge messages. Third, the architecture in proposed VES can efficiently save the memory usage in channel values, and it has about 75% reduction when the number of nm is equal to 32. Forth, we use EMS decoding algorithm which is more com-plicated than Min-Max decoding algorithm but it has better decoding performance. Although we use very short code length (672 bits), the decoding performance are still competitive with other designs based on the higher finite field size (GF(26)). Especially when choosing nm=32 to implement, the decoding performance loss is negligible (< 0.1 dB) compared with FFT-SPA
decoding algorithm. Fifth, the hardware efficiency of our design is better than other existing works, and it has at least 4.3 times improvement.
Based on the improvements in our design above, we can really enhance the hardware effi-ciency of the non-binary LDPC decoder, and have well enough decoding performance. Using a 90-nm CMOS process, we implemented the proposed non-binary LDPC decoder with nm=8, and the throughput can reach over 100 Mbps.
5.2 Future Work
In proposed decoder, we double the throughput and reduce the memory usage by the code property that the column degree is 2. Applying these techniques, non-binary LDPC decoder design for two different size of nm (8 and 32) are provided. In non-binary LDPC decoding algorithm, the larger size of nm can have better decoding performance, but the computational complexity and memory usage are also increased. Based on the consideration of hardware cost, we choose the decoder with nm=8 to implement, but its decoding performance is worse than the case of nm=32 about 0.4 dB. For this reason, we can try to figure out some approaches to decrease the performance loss when changing the value of nm. Besides, as we only store half edge messages in our decoder in layered scheduling, grouping and processing order are important in decoding. To avoid the memory collision problems (in 3.6.3.1), we rearrange the processing order by manual operation. For more general implementation, the relation between the accessing order of groups and the number of parallelism in the decoder should be made by a valid inference.
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