In this thesis, we focus on the specific ASIC design for the effective pipeline FFT/IFFT processor. Considering the hardware-orientated architecture for most efficiency, the specific FFT/IFFT processor not only minimizes the computation complexity and area cost, but also increase the hardware utilization rate with an appropriate throughput rate for different applications. For the purpose of demonstrating the effective computations in different real-time applications, four different standards have been considered, which include DTMF [12-15], MIMO-OFDM WLAN [22, 23], DVB-T [27, 28] and next generation mobile multimedia standards [5-7, 44].
For the high channel density DTMF systems, one new recursive DFT/IDFT algorithm and architecture based on a hybrid of input strength reduction scheme, the Chebyshev polynomial and register-splitting scheme is devised in this framework. The analyzed results show that the proposed VLSI algorithm leads to the fewest computation cycle and the highest throughput rate. Moreover, the proposed 212/106-point recursive DFT/IDFT chip design has been successfully implemented in 0.13 µm CMOS technology and possesses the power-efficiency consumption of 9.77 uW@20 MHz at 1.2V supply voltage for each channel. These features guarantee that the proposed high-throughput and power-efficient VLSI architecture is amenable to high channel density DTMF systems.
For the MIMO-OFDM system, we proposes a hardware-orientated approach for high efficiency to minimize the complex multiplicative complexity, area cost and achieve 100% butterfly utilization with an appropriate throughput rate. By adopting the proposed R8-FFT unit combined with the MAW method, two efficient serial blockwise type 64-point FFT/IFFT processors are constructing for the 2×2 and 4×4 MIMO-OFDM WLAN systems. For the 2×2 MIMO-OFDM system, the proposed R28MDF design has the best performance in terms of lowest complex multiplicative complexity, appropriate throughput rate of 2R, highest butterfly utilization and the fewest complex multipliers, when compared with other existing 64-point FFT/IFFT processor architectures. For the 4×4 MIMO-OFDM system, the proposed R28MDC outperforms existing FFT/IFFT pipeline processor architectures and has the lowest complex multiplicative complexity, an appropriate throughput rate of 4R, highest utilization rate (100%) of all components and the lowest hardware cost. According to the IEEE 802.11n standard [23], execution time for the 128-point and 64-point FFT/IFFT processor with 1–4 simultaneous data sequences must be calculated within 3.6 or 4.0 µs. In total, eight operational modes of the FFT/IFFT
processor are required in the IEEE 802.11n standard. The effective reconfigurable FFT/IFFT processor [73] supports eight operational modes in the IEEE 802.11n standard, consumes small hardware and little power, is easily reused, and is an important topic for future work.
For the long-length based FFT computations, we develops two high effective R42SDF and R43SDF pipeline VLSI architectures that support the long-length FFT/IFFT computations. The proposed R43SDF pipeline FFT/IFFT architecture has lower multiplicative complexity and higher hardware utilization rate with smaller cost than R42SDF and other pipeline architectures. Following with fixed-point analysis in 40dB AWGN environment, the proposed R42SDF and R43SDF based 4096-point FFT/IFFT designs are successfully implemented in 0.13 µm CMOS technology with an internal word-length of 14 and 13-bits, respectively. The proposed R42SDF and R43SDF based design have a low power consumption of 6.3725 and 5.985 mW @20 MHz at 1.2V supply voltage. Thus, these features ensure that the proposed R43SDF pipeline processor design certainly meets the high effective VLSI architecture.
For the next-generation mobile applications, we develops a triple-mode reconfigurable pipeline R42SDF VLSI architecture that supports the 256-point FFT/IFFT and 8×8 2-D DCT computations. The comparison results demonstrate that the proposed R42SDF pipeline FFT/IFFT architecture has a lower hardware cost and higher utilization than R22SDF and other pipeline architectures. Following the fixed-point analysis the proposed 256-point FFT/IFFT/8×8 2-D DCT chip design is successfully implemented in 0.13µm CMOS technology with an internal wordlength of 13 bits. This design has a power consumption of 22.37 mW@100 MHz at 1.2V supply voltage. These features ensure that the proposed reconfigurable processor design is certainly amenable to the next-generation mobile communications. The upcoming fourth-generation wireless system requires the simultaneous application of many computing algorithms including MPEG-4 AVC [83] and Walsh transform [84], in the same handheld device. Then, the reconfigurable hardware core for supporting more transforms is a significant topic for future work. Furthermore, the fixed word-length analysis for each building block to reduce more hardware cost is also important future investigations. According to the comprehensive comparisons and implementation results, we could provide that the proposed RDFT, R28MDF/R28MDC, R42SDF/ R43SDF and Triple-Mode designs achieve the high effective advantages for DTMF, MIMO-OFDM WLAN, DVB-T and next-generation applications.
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Appendix A
The Transfer Function between 8×8 2D SFFT and 8×8 2D DCT
Equation (90) reveals that the 2D DCT result of X[k1,k2] can be derived from the 8×8 2D SFFT with a time-domain shift of 1/4 samples.
∑ ∑ ⋅ ⋅ the second half output of the 8×8 2D-shifted SFFT can be calculated as
∑ ∑ ⋅ ⋅ product of two real parts of the twiddle factors 1 4) 1
( 1
Furthermore, the real value of YS(k1,k2) and the imaginary value of YS(8−k1,k2) can be
The 8×8 2D DCT result can thus be expressed as a subtraction of the imaginary value of YS(8−k1,k2) from the real value of YS(k1,k2) and. respectively, can then be obtained as below:
{
Re[ ( , )] Re[ (8 ,8 )]}
computation as above.VITA
姓名： 余遠渠 性別： 男
生日： 民國 61 年 10 月 7 日 籍貫： 台灣省桃園縣
學歷：
1. 民國 78 年 6 月苗栗市建台高級中學畢業
2. 民國 82 年 6 月私立逢甲大學自動控制工程系學士畢業 3. 民國 84 年 6 月私立逢甲大學自動控制工程系碩士畢業 4. 民國 92 年 9 月國立交通大學電機與控制工程學系博士班 經歷：
1. 民國 86 年 6 月~民國 86 年 10 月(4 個月): 楊宇科技—專案經理 2. 民國 88 年 9 月~民國 90 年 2 月(1 年 5 個月):
宏碁電腦—數位電路設計, 資深工程師 3. 民國 90 年 2 月~民國 97 年 1 月(6 年 11 個月):
義隆電子—數位 IC 設計,副理 4. 民國 97 年 1 月迄今(3 個月): 智微科技—數位 IC 設計,經理
PUBLICATION LISTS 期刊部分
期刊部分 期刊部分 期刊部分：：：：
[1] Lan-Da Van, Chin-Teng Lin and Yuan-Chu Yu, “VLSI Architecture for the Low-Computation Cycle and Power-Efficient Recursive DFT/IDFT Design,” IEICE Trans. on Electronics, Information and Communication Engineers, Vol. E90-A, No.
8, Aug. 2007.
[2] Chin-Teng Lin, Yuan-Chu Yu and Lan-Da Van, “Cost-Effective Triple-Mode Reconfigurable Pipeline FFT/IFFT/2-D DCT Processor, “ IEEE Trans. on VLSI, Accepted, 2007.
[3] Chin-Teng Lin and Yuan-Chu Yu, “Design of an Effective Pipeline FFT/IFFT Processor, “ International Journal of Electrical Engineering (IJEE), Accepted, 2008.
會議論文 會議論文 會議論文
會議論文部分部分部分部分：：：：
[1] Lan-Da Van, Yuan-Chu Yu, Chun-Ming Huang, Chin-Teng Lin, "Low computation cycle and high speed recursive DFT/IDFT: VLSI algorithm and architecture," in Proc. IEEE Workshop on Signal Processing Systems (SiPS 2005), Nov. 2005, pp.
579-584, Athens, Greece.
[2] Chin-Teng Lin, Yuan-Chu Yu, and Lan-Da Van, “A Low Power 64-Point FFT/IFFT Design for IEEE 802.11a WLAN Application”, IEEE Int. Symp. on Circuits and Syst.
2006 (ISCAS 2006), May 21-24, 2006.
[3] Chin-Teng Lin, and Yuan-Chu Yu “Cost-Effective Pipeline FFT/IFFT VLSI Architecture for DVB-T System”, National Symp. on Telecommunications 2007 (NST 2007), Oct. 28, Taipie, Taiwan.
申請之專利 申請之專利 申請之專利
申請之專利部分部分部分部分：：：：
[1] Chin-Teng Lin, Lan-Da Van and Yuan-Chu Yu, “可正反轉共用之遞迴式離散傅力葉 處理器單核心裝置及其應用, “0007-158, 公告中, 2007.
[1] Chin-Teng Lin, Lan-Da Van and Yuan-Chu Yu, “可正反轉共用之遞迴式離散傅力葉 處理器單核心裝置及其應用, “0007-158, 公告中, 2007.