Contributions

For the purpose of supporting these four applications, six ASIC based pipeline processors, namely recursive DFT/IDFT (RDFT) based processor, radix-2/8 multiple-path delay feedback (R28MDF) based processor, radix-2/8 multiple-path delay commutator (R28MDC) based processor, radix-4² single-path delay feedback (R4²SDF) based processor, radix-4³ single-path delay feedback (R4³SDF) based processor and reconfigurable triple-mode FFT/IFFT/2-D DCT processor, have been presented in this thesis. The contributive descriptions are presented as below:

1. RDFT Design: Based on the proposed RDFT architecture, one high-throughput (i.e. high channel density) and power-efficient DTMF detector has been proposed. For the purpose of achieving the high power efficiency, we perform the bit level SNR simulation to decide the best configuration for the DTMF detector system. The results show that the proposed design only needs 9-bit word-length, which is one-bit less than the second order Goertzel structure, to land the satisfactory resolution under 15 dB SNR environment. In this paper, the resulting DTMF detector uses 12-bit word-length, where the additional 3 bits are used for design margins so as to obtain better performance. On the other hand, the novel design saves 4-bit cost compared with the 16-bit based DSP processor design [12]-[14]. In summary, the proposed DTMF structure not only saves more area cost, but also reduces the power consumption due to the register-splitting

scheme [51] and a smaller word-length requirement. Most importantly, the computation cycles can be reduced to 50% and thus a double throughput rate and channel density can be easily obtained without increasing the operation frequency. Our proposed DFT/IDFT chip is able to offer over 128-channel telephone signals for the high channel density DTMF detector [16] without any DSP processor inside. Each channel consumes 9.77 uW under 1.2V@20 MHz in TSMC 0.13 1P8M CMOS process. This is a significant contribution, as the high channel density and low power characteristics are demanded for the communication systems.

2. R28MDF and R28MDC Design: This investigation presents two new efficient designs, R28MDF based and R28MDC based FFT/IFFT processors for the 2×2 and 4×4 multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) wireless LAN (WLAN) system, respectively. The novel radix-2/8 algorithm reduces the half constant multiplier requirement in the proposed retrenched 8-point FFT (R8-FFT) unit compared with that of the conventional radix-2/8 algorithm, and has low multiplicative complexity as a radix-8 based algorithm. By applying the R8-FFT unit combined with the proposed multiplication-after-write (MAW) method, the R28MDF and R28MDC architectures resulted in 100% butterfly utilization and an appropriate throughput rate with few hardware resources for the 2×2 and 4×4 MIMO-OFDM applications, respectively. Implementation results indicate that two chips consume only 19.42mW and 23.57mW under 1.2V@20 MHz in a TSMC 0.13µm 1P8M CMOS process. The comparison results among the existing 64-point FFT/IFFT processor architectures are comprehensively discussed. The architecture analyses and chip implementation indicate that the proposed FFT/IFFT processor architectures are suitable for MIMO-OFDM WLAN systems.

3. R4²SDF and R4³SDF Design: In this investigation, we proposes the novel radix-4² and radix-4³ algorithms with the low computational complexities of the radix-16 and radix-64 algorithms and the low hardware requirement of the radix-4 algorithm. Base on the multiplierless radix-4 butterfly structure, the proposed R4²SDF design and R4³SDF design support the 4096-point FFT/IFFT computations. Moreover, the retrenched constant multiplier and eight-folded complex multiplier structures are adopted to decrease the multiplier cost and the coefficient ROM size with the complex conjugate symmetry rule and subexpression elimination technology. To further decrease the chip cost, a finite word-length analysis is provided to indicate that the proposed R4²SDF and R4³SDF architectures only require 14 and 13-bit internal word-length to achieve 40dB

SNR performance in the 4096-point FFT/IFFT computation. The comprehensive comparison results indicate that the proposed R4³SDF design has the smallest hardware cost and the highest hardware utilization among the tested architectures for the FFT/IFFT computation, and thus has the highest efficiency. The implementation results show that the proposed R4²SDF and R4³SDF based 4096-point pipeline FFT/IFFT processors only consumes 6.3725 and 5.985 mW@20 MHz at 1.2V supply voltage in TSMC 0.13 µm CMOS process.

4. The triple-mode reconfigurable FFT/IFFT/2D-DCT Design: Applying the R4²SDF architecture with the specific linear mapping of common factor algorithm (CFA), the proposed triple-mode design supports both 256-point FFT/IFFT and 8×8 2-D DCT modes following with the high efficient feedback shift registers architecture. The segment shift register (SSR) and overturn shift register (OSR) structure are adopted to minimize the register cost for the input re-ordering and post computation operations in the 8×8 2-D DCT mode, respectively. Moreover, the retrenched constant multiplier and eight-folded complex multiplier structures are adopted to decrease the multiplier cost and the coefficient ROM size with the complex conjugate symmetry rule and subexpression elimination technology. To further decrease the chip cost, a finite wordlength analysis is provided to indicate that the proposed architecture only requires a 13-bit internal wordlength to achieve 40dB SNR performance in 256-point FFT/IFFT modes and high digital video (DV) compression quality in 8×8 2-D DCT mode. The comprehensive comparison results indicate that the proposed cost effective reconfigurable design has the smallest hardware requirement and largest hardware utilization among the tested architectures for the FFT/IFFT computation, and thus has the highest cost efficiency. The derivation and chip implementation results show that the proposed pipeline 256-point FFT/IFFT/2-D DCT triple-mode chip consumes 22.37mW@100 MHz at 1.2V supply voltage in TSMC 0.13µm CMOS process, which is very appropriate for the RSoCs IP of next-generation handheld devices.