This primary research questions that contained two issues of IEEE 802.16e FEC in this thesis were (a) the research in convolution code with tail-biting and implementation on the VCP of TI’s C6416 for the WiMAX applications, and (b) the max-log-MAP decoding research of the CTC and implementation on DSP.
In the first issue, we first analyzed and studied TI EDMA to employ the VCP based on convolution code with tail-biting in AWGN. In our implementation, the convolution coding gain in AWGN was less than theoretic value by 0.1 to 2.6 dB. When we converted the fixed-point to the VCP application, the performance was almost the same and we could just use S2.5 for BM truncation to implement the decoder. Finally, in our decoder with the VCP, we can approach data rates between 6.2 and 9.2 Mbps for CCS profile. However, we can also utilize the 3L timer to measure, approaching data rates about between 2.6 and 3.5 Mbps.
Therefore, under CCS and 3L, as the measurements indicate the decoder processing rates are improved significantly by about 9.8 and 4.7 times, respectively, with use of VCP.
In the second issue, we first evaluated the performance of CTC and compared the results with the numerical results. The coding gain of CTC was much better than convolution code.
Then we focused on max-log-MAP decoding algorithm. Then we converted the floating-point
to fixed-point, and we could use S12.3 and S11.4 to implement the decoder for QPSK and 16QAM (64QAM), respectively. In conclusion, in the encoder, we can approach data rates between 7.7 to 9.1 Mbps and in our decoder with 4 iterations, we can approach data rate about 300K bps.
In the future work, further optimization of the programs may be possible. For example, if we can parallelize the execution of the peripheral functions and the VCP, we may get approach an information data rate of about 6 Mbps in decoding under 3L. However the interested readers can refer to “Continuous Decoding” mechanism in [21] to study.
In CTC, there are three possible methods to enhance our DSP implementation. First, we may rewrite our code in our CTC, there are too much dependence to execute for Alpha and Beta loop. These execute too many cycles and cause software pipelined worse. However, one possible way is to examine every function and loop to improve its software pipelinability.
Second, if we need further reducing complexity by max-log-MAP decoding algorithms, [28] is one of the references. Third, we can examine the TI’s C6416 TCP (Turbo -decoder coproces-sor) [15]. The TCP is a programmable peripheral for decoding IS2000/3GPP turbo code, integrated in into C6416 DSP. The coprocessor operates two modes, standalone processing mode and share processing mode, which are detailed discussed in [15]. It may be of inter-est for using TCP to be helpful in raising the decoding speed, but how to process the IO relationship for double-binary circular recursive systematic convolutional code on the TCP application is a tough problem.
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