Conclusions

Table 6-1 Summary statement of rising time and falling time dependence of gate AC signal for N-type………...…………. 97 Table 6-2 Summary statement of rising time and falling time dependence of gate

AC signal for P-type………. 97

Chapter 1

Introduction

1.1 Overview of Low-Temperature Polycrystalline Silicon Thin Film Transistors ( LTPS TFTs )

Nowadays, the amorphous silicon (a-Si) thin film transistors (TFTs) are commonly used to be the switches of the pixel in active matrix liquid crystal displays (AMLCDs).

Fig. 1-1 shows the block diagram of active matrix display. All the driver chips are buried together with the other application-specified ICs on PCB because the current driving capacity of a-Si TFTs is not good enough for the system integration. However, the integration of driver circuitry with display panel on the same substrate is very desirable not only to reduce the module cost but to improve the system reliability.

Fig. 1-1 The block diagram of active matrix display

For this reason, low-temperature polycrystalline silicon (poly-Si) thin film transistors (TFTs) have attracted much attention because they have been used very successfully for active matrix displays, such as active matrix liquid crystal displays (AMLCDs) and active matrix organic light emitting displays (AMOLEDs). Except large area displays, poly-Si TFTs have been applied into some memory device such dynamics random access memories (DRAMs), static random access memories (SRAMs), and have great potential for 3-dimension IC applications.

Compared with conventional a-Si TFTs, the field effect mobility of poly-Si TFTs is much higher. In polysilicon film, the carrier mobility larger than 100cm²/Vs can be easily achieved, which is about 100 times larger than that of the conventional amorphous-silicon TFTs (typically below 1cm²/Vs). Higher field effect mobility means transistors can provide higher driving current. The higher driving currents can allow the pixel-switching element TFT’s dimension shrinkage, resulting in higher aperture ratio and lower parasitic gate-line capacitance for improved display performance. Besides, the superior mobility performance allows the integration of both the active matrix pixel switching elements and the peripheral driving circuitry on the same glass substrate, which brings the era of system-on-glass (SOG) that will include a memory, central processing unit (CPU), and display on the same glass. In this way, the process complexity can be greatly simplified and manufacturing cost can be substantially reduced. The ability of fabricating high-performance low temperature poly-Si (LTPS) TFTs enables their use in a wide range of new applications. Therefore, there is a great interest in improving the performance of LTPS TFTs.

In comparison with signal-crystalline silicon, poly-Si film contains many grain boundary defects and intra-grain defects. The order of poly-Si grain size is about 0.3um.

At present, when poly-Si TFTs are used in LCD applications, the minimum channel length is typically much larger than 3µm, and therefore a large number of grain boundaries are

present in the channel. Electrons are scattered at the grain boundaries or trapped by the interface states, leading to lower mobility than in single crystal silicon. Much effort has been made to increase the performance of LTPS TFTs. Crystallization of a-Si thin films has been considered the most critical process for fabricating high-performance LTPS TFTs.

Among various crystallization technologies, excimer laser crystallization has become the mainstream technology for mass production of flat panel displays (FPDs) because of high throughput, low temperature process compatible with glass substrate, and formation of high-quality poly-Si.

In summary, it is expected that the poly-Si TFTs will become increasingly important in future technology, especially when the 3-D circuit integration and SOG era is coming.

There are lots of interesting and important topics that are worthy to be researched.

1.2 Review of Degradation Model for TFT under AC Stress

In order to realize the new applications for LTPS TFTs, we have to improve the performance such as enhancing mobility, decreasing the threshold voltage of TFTs, and shrinking the TFTs size. However, the poly-Si TFT reliability improvements are as critical for the insurance of product lifetime. Therefore, reliability testing and understanding of reliability mechanisms become very necessary.

In previous reports, Toyota et al. proposed that mobile carriers are able to follow the transient variation of gate voltage while the electrons trapped in the midgap state aren’t. In addition, Uraoka et al. attributed the dominant AC degradation mechanism to hot electrons generated by trapped electrons exposed to the high electric field and gain energy from the electric field during AC stress. The mechanism was analyzed by using a pico-second

emission microscope and device simulation to examine the transient current experimentally and theoretically, respectively.

The earlier degradation model under AC stress is described as follow. As for the N-type TFTs, when the gate voltage is high of Vg=15V (ON state), the electrons gather to form a channel, as shown in Fig. 1-2 (a). When the gate voltage drops from Vg=15V to -15V (ON→OFF), the electrons in the channel move rapidly to the source and drain, as shown in Fig. 1-2 (b). Some of the trapped electrons are exposed to the high electric field and gain energy from the field. Hot electrons are generated at this moment and form electron traps, as shown in Fig. 1-2 (c), and a density of state (DOS) in tail edge of poly-Si is increased by the hot electrons.

As for the P-type TFTs, when the gate voltage is low of Vg=-15V (ON state), the holes gather to form a channel, as shown in Fig. 1-3 (c). When the voltage transition from low to high of Vg=-15V to 15V (ON→OFF), the holes in the channel move rapidly to the source and drain, as shown in Fig. 1-3 (b). Carriers gain energy from this electric field and become hot carriers. Therefore, more hot electrons are generated which causes trap formation at the grain boundaries around the drain edge, as shown in Fig. 1-3 (a).

ON

Fig. 1-2 A schematic diagram for degradation model of the N-type TFT

Vg=+15V

Fig. 1-3 A schematic diagram for degradation model of the P-type TFT

1.3 Motivation

The Poly-Si TFTs displays with integrated driving circuits have recently been developed. At present, the poly-Si TFTs are the best candidate to realize system on panel (SOP) and are widely considered for AMLCDs and active matrix organic light-emitting diodes (AMOLEDs).

The reliability mechanisms of LTPS TFTs under DC (direct current) bias stress and AC stress which source drain were ground have been widely discussed. However, up to now, the reliability of LTPS TFTs under gate AC stress with drain bias has been paid much less attention, shown in Fig. 1-4. In previous studies regarding AC stress, the source and drain were ground to avoid the DC effect during dynamic stress. However, when the gate of the TFT is under dynamic operation, the drain-source voltage is usually present. For example, the pixel TFTs driven by multi level gate scanning waveforms can be subject to the off-region AC stress at gate with DC drain bias.

Last, CMOS technology is necessary for driving circuits, which means that both the understanding of the reliability of N-type and P-type LTPS TFTs are necessary. Therefore, it is extremely important to understand the degradation mechanisms of N-channel and P-channel LTPS TFTs under AC stress.

Fig. 1-4 Previous researches of LTPS TFT reliability

For the previous work in our lab (thesis of Wei-Lun Shih), it is not noticed that the applied gate signals overshoot beyond the target value we have set. Based on those results, it is found that the signal of Vgh is higher and Vgl is lower than the values we set, as shown in Fig. 1-5(a). The effect of overshooting could introduce other effect of the study of reliability.

Therefore, in this study, the overshooting is carefully avoided for the applied gate signals, as shown in Fig. 1-5(b). The degradation behavior can be free from the overshooting effect. Thus, we re-examine the degradation of N-channel and P-channel LTPS TFTs under off-region AC stress conditions with various drain bias with proper apparatus setup. The stress conditions including swing range, and falling/rising times of the gate pulse, were discussed to verify the degradation mechanism under gate AC stress

with drain bias.

Fig. 1-5(a) the verification of output waveform with overshooting

Fig. 1-5(b) the verification of output waveform without overshooting

1.4 Thesis Organization

Chapter 1 Introduction

1.1 Overview of Low-Temperature Polycrystalline Silicon Thin Film Transistors (LTPS TFTs)

1.2 Review of Degradation Model for TFT under AC Stress 1.3 Motivation

1.4 Thesis Organization

Chapter 2 Experimental Procedures

2.1 Procedures of Fabrication of LTPS TFTs 2.2 Extraction Method of Device Parameters 2.3 C-V Measurements

2.4 Stress Conditions

2.4.1 Gate Pulse Stress with Drain and Source Ground 2.4.2 Gate Pulse Stress with Drain Bias and Source Ground

Chapter 3 Degradation for Poly-Si TFT under Gate Pulse Stress with Drain and Source Ground

3.1 Frequency Dependence

3.2 Gate Voltage Leveling Dependence

3.3 Rising Time and Falling Time for Vg of ON and OFF Region 3.4 Rising Time and Falling Time for Vg in the OFF Region

Chapter 4 Degradation for N-type Poly-Si TFT under Gate Pulse Stress

with Drain Bias

4.1 Frequency Dependence 4.2 Effect of Drain Bias

4.2.1 Vg in ON and OFF region 4.2.2 Vg in the OFF region 4.3 Effect of Gate Voltage Range 4.4 Other Effects

4.4.1 Effect of Rising Time 4.4.2 Effect of Falling Time 4.5 Results and Discussions 4.6 Summary

Chapter 5 Degradation for P-type Poly-Si TFT under Gate Pulse Stress with Drain Bias

5.1 Effect of Drain Bias

5.2 Effect of Gate Voltage Range 5.3 Other Effects

5.3.1 Effect of Rising Time 5.3.2 Effect of Falling Time 5.4 Results and Discussions 5.5 Summary

Chapter 6 Conclusions

Chapter 2

Experimental Procedures

2.1 Procedures of Fabrication of LTPS TFTs

LTPS TFTs used in the experiment were the conventional top-gate structure and fabricated on the glass substrates. The cross-section views of N-channel and P-channel LTPS TFTs are shown in Fig 2-1 and Fig. 2-2 respectively. The basic process flow is described as follows. Firstly, the buffer oxide and a-Si:H films were deposited on glass substrates by the PECVD system. Then, XeCl excimer laser was used to crystallize a-Si:H film followed with poly-Si active area definition. Subsequently, gate insulator was deposited by PECVD. The thickness of gate oxide is 650Å. Next, the metal gate formation and source/drain doping were performed. Dopant activation and hydrogenation was carried out after interlayer dielectric deposition. Finally, contact holes formation and metallization were performed to complete fabrication work. The lightly doped drain (LDD) structure was used in the N-channel TFTs to enhance hot carrier endurance while not used in P-type devices. The width/length of the TFT was 20μm/5μm.

Fig. 2-1 The cross-section views of N-channel LTPS TFTs with LDD structure

Fig. 2-2 The cross-section views of P-channel LTPS TFTs

2.2 Extraction Method of Device Parameters

The field effect mobility (Mu, µFE) is derived from the maximum value of the transconductance g_m, which can be expressed as:

1 2

C_ox is the gate capacitance per unit area, W is channel width,

L is channel length,

Vth is the threshold voltage.

If the drain voltage V_D is much smaller as compared with (V_G−V_th) (i.e. V_D << V_G - Vth), then the drain current can be approximated as:

D And the transconductance is defined as:

D

Therefore, the field effect mobility can be expressed as:

g m

In other words, the field-effect mobility can be extracted by taking the maximum value of the gm into (2-4) when VD = 0.1V.

For most of the researches on TFT, the constant current method is widely-used to determine the threshold voltage (Vth). The threshold voltage in the thesis is determined from this method, which extracts V_th from the gate voltage at the normalized drain current

N D eff eff

I =I /(W -L )=10nA for ｜VDS｜=0.1V.

(2-2)

2.3 C-V Measurements

Since the I-V transfer curves show the entire characteristics of the whole channel and may not distinguish the dominant mechanism, C-V measurements were further employed to investigate the asymmetry electric field at the source and drain of TFTs during the stress.

The C-V curves of the normalized gate-to-drain capacitance (CGD) and the normalized gate-to-source capacitance (C_GS) before and after stress at different stress conditions were measured with the Agilent 4284Aprecision LCR meter. The normalized capacitance is the ratio of the measured capacitance to a constant of 60fF, which is the gate oxide capacitance of the TFT under test.

Since it is difficult to observe the defect position in TFTs with the I-V characteristic, the C-V measurement is used to examine the information about position and type of degradation in the device after stress. For instance, if carriers are trapped by defects, C-V curve stretch out slightly, or if states are generated additionally, C-V curve increase somewhat in the depletion region. Besides, the C-V curves are helpful to identify whether the dominant mechanism of degradation is the increase of fixed charges or trap states.

2.4 Stress Conditions

The Agilent 4156A semiconductor parameter analyzer with pulse generator was used to measure the I-V curve and stress the device with different conditions. The basic parameters of AC signal consists of frequency (F), signal high level (Vgh), signal low level (Vgl), high-level time (T_Vgh), low-level time (T_Vgl), rising time (Tr), and falling time (Tf). Fig 2-3 shows the waveform of the AC signal. In AC signal, the definition of individual parameter is given as above:

T = Tr + T_vgh + Tf + T_vgl (2-5) F = 1/T Duty ratio = (Tr + T_vgh)/T (2-7) where T is the signal period.

Fig. 2-3 Waveform and definition of the AC signal

2.4.1 Gate Pulse Stress with Drain and Source Ground

Under AC stress, pulse voltage was applied to the gate electrode and source and drain were grounded, which is shown in Fig. 2-4. The standard stress condition in the experiment is the gate voltage swing of -15V to 15V, F = 500 kHz, Tr and Tf are both 100ns, and duty ratio is 50%. These parameters can be adjusted and then various stress conditions on the gate electrode were performed to examine the reliability of LTPS TFTs.

To investigate which parameter of the stress parameters dominates the degradation of the N-channel and P-channel TFTs transfer characteristics, we will make four experiments.

(2-6)

Firstly, we change frequency from 0.5KHz to 500KHz. Secondly, we change Vgh and Vgl of AC signal fixed amplitude of 15V at one time, called Vg leveling. Thirdly, we will change Tr and Tf from 100ns to 700ns for gate swing range of -15V to 15V. And finally, we want to understand the effects of Tr and Tf for the gate swing in the depletion region.

The experimental conditions are shown in Table 2-1 and Table 2-2. It will be investigated for reliability testing in the chapter 3.

Fig. 2-4 TFT under AC stress with source and drain grounded

Table 2-1 The experiment condition forms for N-type under gate pulse with drain and source ground

Table 2-2 The experiment condition forms for P-type under gate pulse with drain and source ground

2.4.2 Gate Pulse Stress with Drain Bias and Source Ground

In the second part of experiment, pulse voltage was applied to the gate electrode in off region with drain DC while source is grounded, which is shown in Fig. 2-5. The standard stress condition in the experiment includes the gate voltage swing of -15V to 0V for N-type, 0V to 15V for P-type, F = 500 kHz, Tr and Tf are both 100ns, and duty ratio is 50%. These parameters can be adjusted to perform then various stress conditions.

Firstly, V_D is changed from 0V to 20V for N-type and 0V to -20V for P-type, to study the effect of drain voltage under gate AC stress. Secondly, we change Vgl from -5V to -20V for N-type and Vgh from 5V to 20V for P-type, to investigate the effect of gate voltage range. Thirdly, we change Tr and Tf from 100ns to 700ns, to understand the transient time dependence. The stress conditions in this thesis are summarized in Table 2-3 and Table 2-4. It will be investigated for reliability testing in the chapter 4 and chapter 5.

Fig. 2-5 TFT under AC stress with drain bias and source ground

Table 2-3 The experiment condition forms for N-type under gate pulse with drain bias and source ground

Table 2-4 The experiment condition forms for P-type gate pulse with drain bias and source ground

Chapter 3

Degradation for Poly-Si TFT under Gate Pulse Stress with Drain and Source Ground

3.1 Frequency Dependence

Dependence of the device degradation on frequency for N-channel and P-channel TFT is shown in Fig. 3-1(a) and Fig. 3-1(b). The degradation are respectively expressed as the ratio of increased and decreased mobility (µ) for N and P-channel TFTs to their initial mobility (µ0). µ0 and µ are derived from the maximum transconductance at the drain voltage of 0.1 V (N-channel) and -0.1V (P-channel) before and after stress. For N-channel TFT, when the frequency increases from 0.5KHz to 500KHz, the mobility decreases. For P-channel TFT, when the frequency increases, the mobility slightly increases.

The changes are re-plotted with the number of pulses for N-channel and P-channel TFT , as shown in Fig. 3-2(a) and Fig. 3-2 (b). Independent of the frequency, the degradation of all lines exhibits almost the universal relationship with the number of pulses. The figure clearly indicates the relationship between the degradation and the repetition number and the independence of the frequency. In other words, the degradation arisen by the unchanging voltage can be ignored.

0.1 1 10 100 1000

Fig. 3-1(a) Frequency dependence of degradation of N-channel TFT under gate pulse with drain and source ground

0.1 1 10 100 1000

Fig. 3-1(b) Frequency dependence of degradation of P-channel TFT under gate pulse with drain and source ground

10⁴ 10⁵ 10⁶ 10⁷ 10⁸

Fig. 3-2(a) Dependence on the number of pulse repetitions of N-channel TFT under gate pulse with drain and source ground

10⁴ 10⁵ 10⁶ 10⁷ 10⁸

Fig. 3-2(b) Dependence on the number of pulse repetitions of P-channel TFT under

3.2 Gate Voltage Leveling Dependence

The range of the gate pulse swing is separated into two parts according to the threshold voltage, as shown in Fig. 3-3(a) and Fig. 3-4(a). In the ON region, the channel is formed, while in the OFF region, the channel was fully depleted. Fig. 3-3(b) and Fig. 3-4(b) clearly indicates that the degradation of mobility strongly depends on the levels of the gate voltage. For the gate pulse swing in the ON region, the degradation is very small, however, that for the gate pulse swing fully in the OFF region become large. It is because the transient electrical field is high in the OFF region, but that is very low in the ON region.

Carriers can gain energy from high electrical field and become hot carriers, and the traps are generated.

Fig. 3-3(a) Swing region for N-channel

Fig. 3-3(b) Dependence of degradation on swing region for N-channel TFT

Fig. 3-4(a) Swing region for P-channel

Fig. 3-4(b) Dependence of degradation on swing region for P-channel TFT

3.3 Rising Time and Falling Time for Vg of ON and OFF Region

For N-channel TFT, the transient time dependence for the degradation was examined as shown in Fig. 3-5. During the variation of rising time Tr from 100ns to 700ns with a fixed Tf of 100ns, no significant change in µ/µ₀ was observed as shown in Fig. 3-5(a). On the contrary, the degradation depended strongly on the falling time Tf as shown in Fig.

3-5(b). The degradation is remarkably accelerated with the decrease of the falling time from 700ns for 100ns for a fixed Tr of 100ns. In the case of changing rising time, the gate voltage varies from OFF region to ON region, and the mobile carriers are sited at so low electrical field that no device degradation is formed. But in the case of changing falling time, the gate voltage varies from ON region to OFF region, some carries remain in the channel and are subjected to the high electrical field becoming hot carries.

Fig. 3-5(a) Degradation of µ/µµ/µµ/µµ/µ₀₀₀₀ in N-channel TFT under AC stress with Vg = -15V to 15V measured for various rising times Tr and for Tf = 100ns.

Fig. 3-5(b) Degradation of µ/µµ/µµ/µµ/µ₀₀₀₀ in N-channel TFT under AC stress with Vg = -15V to 15V measured for various rising times Tf and for Tr = 100ns.

For P-channel TFT, the transient time dependence for the degradation was also studied.

The dependence of the mobility change on rising time and falling time is shown in Fig.

3-6(a) and Fig. 3-6(b), respectively. The change was accelerated for a variation in rising time; however, the change was not affected by the falling time. In the case of changing

3-6(a) and Fig. 3-6(b), respectively. The change was accelerated for a variation in rising time; however, the change was not affected by the falling time. In the case of changing

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