In this chapter, conclusions of this thesis are made first, and then the future works of this thesis are proposed.
5.1 Conclusions
As the demand for the enlarging program size due to the requirement of more program functionalities and the evolution of mixed-width ISA architectures in embedded systems, a register allocation and assignment algorithm for mixed-width ISA will become more and more important in the near future. In this thesis, we present two register allocation and assignment algorithms for mixed-width ISA with mode switch by instruction encoding.
The first proposed algorithm, MxBuGCRA, is composed of two passes: the allocation pass is to allocate registers with the consideration of minimizing spill codes, and the assignment pass is to assign register with the consideration of increasing the translation rate of S-Format instructions. The second proposed algorithm, MxPrGCRA, firstly picks variables up in an order which is considered to increase the translation rate of S-Format instructions, and then picks the remaining variables up for minimizing spill codes. Both of these two algorithms try to make efforts on reducing code size while minimizing the number of spill codes by using the sel_profiti function for the former and the SpillCosti function for the latter.
We have conducted experiments to verify the algorithm for a mixed-width ISA processor.
It is found that the code size reduction is achieved 31.89% and 31.90% on average for our algorithms respectively. Meanwhile, the proposed algorithms do efforts on minimizing the generated spill codes. From the experiments, it shows that only 0.24% and 0.23% extra spill codes generated by MxBuGCRA and MxPrGCRA than BuGCRA and PrGCRA, respectively.
55
The last, we also showed that the different results in code size reduction and spill codes for the proposed algorithms by setting the different α values for varies demands.
5.2 Future Works
The future works of this thesis can be put into four dimensions: reducing the runtime I-cache miss rate, obtaining the optimal solution of code size reduction, integrating other optimization techniques, e.g. instruction scheduling, for getting more code size reduction using the proposed algorithms, and modifying the proposed algorithms to match the requirements of other optimization techniques.
The first, we do not take loops into account because our objective is to reduce the program code size rather than the dynamic trace size in this thesis. However, it is a good option to observe while considering the reduction of the runtime I-cache miss rate for further researches.
The second, in order to obtain the optimal solution of code size reduction for the Mixed-width ISA with mode switch by instruction encoding, the methods which are designed for solving NP-Complete problems are good options, e.g., the Integer Linear Programming (ILP) and Partitioned Boolean Quadratic Problem (PBQP). Both of ILP and PBQP formulate problems into equations and solve them to get a unique solution. But the execution time is too slow to be adopted in practice. However, it is a good way to obtain the optimal solutions.
The third, it may have more code size reduction by integrating other optimization techniques for the proposed algorithms. For example, use a pre-instruction scheduling to shorten the live ranges of a program function. Therefore, it may release registers in RegisterSetS at some execution points and make more variables can be assigned in
56
RegisterSetS. But any changes of instruction scheduling will affect the execution performance and register pressure. The scheduling policy should be carefully designed for these considerations.
Finally, we may get some other benefits by doing some modifications to the proposed algorithms. For example, the number of bits-change between instructions may affect the power consumption of the instruction fetch unit and the memory bus. If the RegS-Assignment stage of MxBuGCRA and the LRS Allocation and Assignment pass of MxPrGCRA assign a variable into RegisterSetA when a variable in AllocatedStackS and LRS has no any benefits for code size reduction (i.e. no more instructions can be encoded in S-Format instructions even this variable is assigned in RegisterSetS), it may reduce the bits-change between instructions.
57
References
[1] John Bunda, Don Fussell, W. C. Athas, and Roy Jenevein, “16-bit vs. 32-bit instructions for pipelined microprocessors”, Proceedings of the 20th annual international symposium on Computer architecture, San Diego, California, United States, May 16-19, 1993, p.237-246.
[2] S. Furber, ARM System Architecture, Addison-Wesley. 1996. ISBN 0-201-40352-8.
[3] K. Kissel, MIPS16: High-density MIPS for the embedded market, Tech. report, Silicon Graphics MIPS Group, 1997.
[4] Andes Technology, Andes Instruction Set Architecture Specification, 2008.
[5] Bor-Sung Liang, June-Yuh Wu, Jih-Yiing Lin, Ming-Chuan Huang, Chi-Shaw Lai, Yun-Yin Lien. Ching-Hua Chang, Pei-Lin Tsai, and Ching-Peng Lin, “Instruction set architecture scheme for multiple fixed-width instruction sets and conditional execution”, International Symposium on VLSI Design, Automation and Test, Sunplus Technol. Co., Ltd., Hsinchu, Taiwan, 2005.
[6] Aviral Shrivastava, Partha Biswas, Ashok Halambi, Nikil Dutt, and Alex Nicolau,
“Compilation framework for code size reduction using reduced bit-width ISAs (rISAs)”, ACM Transactions on Design Automation of Electronic Systems (TODAES), January 2006, v.11 n.1, p.123-146.
[7] T. Zeitlhofer, and B. Wess, "A comparison of graph coloring heuristics for register allocation based on coalescing in interval graphs", Proceedings of the 2004 International Symposium on Circuits and Systems, 4: IV-529-32 Vol. 4, May 2004
[8] G. J. Chaitin, “Register allocation and spilling via graph coloring”, Proceedings of the ACM SIGPLAN ’82 Symposium on Compiler Construction, The Association for Computing Machinery, Boston, Massachusetts, June 1982, pages 98–105.
[9] Andrew W. Appel, Modern Compiler Implementation in Java: Basic Techniques,
58
Cambridge University Press, 1997.
[10] Fred C. Chow and John L. Hennessy, “Register allocation by priority-based coloring”, Proceedings of the ACM SIGPLAN ’84 Symposium on Compiler Construction, Montreal, June 1984, pages 222–232.
[11] Jonathan S. Turner, “Almost all k-colorable graphs are easy to color”, Journal of Algorithms, March 1988, 9(1):63–82.
[12] Chris Lattner, and Vikram Adve, “LLVM: A Compilation Framework for Lifelong Program Analysis & Transformation”, Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization, Palo Alto, California, March 20-24, 2004, p.75.
[13] C. Lattner et al, “The LLVM compiler infrastructure”, http://llvm.org.
[14] Preston Briggs, Keith D. Cooper, and Linda Torczon, “Improvements to graph coloring register allocation”, ACM Transactions on Programming Languages and Systems, May 1994, 16(3):428–455.
[15] D. Koes and S. C. Goldstein, An analysis of graph coloring register allocation, Technical Report CMU-CS-06-111, Carnegie Mellon University, March 2006.