4-1 Conclusions
In this study, TiN metal nano-crystal non-volatile memory using high work function p+ poly-Si gate and high-k Al2O3 blocking dielectric layer with multi-gate structure was fabricated on SOI substrate. The TiN nano-crystals are formed by a cyclic deposition of TiN/Al2O3 layers followed by rapid thermal annealing. This method is fully compatible with CMOS technologies. These TiN nano-crystals are readily isolated from each other within an Al2O3 matrix. By inspecting TEM images, it is found that the TiN nano-crystals have diameter of 1~2nm, which is much smaller than the optimum nano-crystal size of 5nm. The fabricated multi-gate TiN nano-crystal non-volatile memory cell has physical gate length of 80nm and fin width of 50nm. Crystallization of Al2O3 is also found in TEM images and it should be responsible for memory characteristic degradation.
As for memory characteristics, device using thicker TiN nano-laminate has larger memory window of about 5V. The program speed is not high because of the small TiN nano-crystals. The strong coulomb blockade and quantum confinement effects limit the trapping efficiency during program. To obtain better retention characteristics, the program and
erase state must be selected carefully. TiN nano-crystal non-volatile memory with good retention of 6% charge loss after 104 sec is demonstrated. Moreover, the variation of retention characteristic is very large even if the process condition and cell size are identical. It is found that the memory cells with higher gate leakage current tend to have poorer retention characteristics. The sample with thicker TiN layer exhibits higher gate leakage current due to the higher stress exerted on the tunneling oxide by the larger TiN nano-crystals. The corner effect of multi-gate structure and the crystallization of the Al2O3 blocking oxide may also affect the gate leakage current. As for reliability, high endurance of 7% degradation after 104 P/E cycles is also exhibited. The small read and gate disturbance characteristics show the multi-gate TiN nano-crystal non-volatile memory cell has potential to adapt the application of NAND type flash memory.
Finally, we presented a novel memory operation scheme. This novel memory operation scheme is done by sensing the level of off-region current. We could control the off-region current to high level (1E-10 A) or low level (1E-12 A) by CHE and BBHH operation. As for memory performance, outstanding retention characteristics almost without degradation after 106 sec can be found. In addition, low operation voltage and large memory window (2 order current level change) can also be obtained. The mechanism of this off-region current change is still researched.
4-2 Future works
In previous chapter, it can be found that the size of TiN nano-crystals is in the range of 1~2nm, which is much smaller than the optimum nano-crystal size of around 5nm. The strong coulomb blockade and quantum confinement effects limit the trapping efficiency during program. In order to increase the program speed and the memory window, the size of TiN nano-crystals must be increased. It is observed in chapter 3 that the program speed and memory window increase dramatically when the TiN layer thickness increases from 0.5nm (sample B) to 0.7nm (sample D). It may because thicker TiN layer has more sufficient material to form larger TiN nano-crystals. For this reason, increasing the size of TiN nano-crystals by increasing the thickness of TiN layers may be a good solution for improving memory characteristics.
It can be observed that because of the thicknesses of charge trapping layer and blocking layer, the gate electrode does not cover the sidewall of the Si-fin thoroughly. By over etching the bottom oxide of the SOI substrate during Si-fin patterning, the sidewall can be fully covered by the charge trapping layer and the gate electrode. It is also expected to increase the number of trapping nodes in one memory cell. The memory characteristics such as P/E speed, memory window, and charge retention may be improved.
The memory cells with higher gate leakage current tend to have poorer retention characteristics and vice versa. It can be directly perceived through the senses that the cells
have bigger gate leakage current increases the loss of stored charge. Therefore, in order to improve the retention characteristics, gate leakage current must be suppressed. It can be done by controlling the film quality carefully or by rounding the sharp fin corner to decrease the electric field near the corner. The crystallization of blocking layer should be also avoided.
New high-k dielectrics with higher crystallization temperature and high enough bandgap should be investigated. Otherwise, the PDA temperature must be lowered. We expect the above changes of structure and process conditions will work and make a great improvement on memory characteristics.
A novel memory operation scheme is mentioned in chapter 3. It has outstanding retention performance, low operation voltage and large memory window. It is a very interesting operation scheme. The mechanism of the switch of the off-region current is still unknown. Other memory characteristics such as endurance and disturbance must be evaluated and the optimum operation biases should be tuned to obtained better performance.
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