Conclusions and Future works
6.1 Conclusions
In this thesis, TFT devices with double-gated nanowire channel structure (DG NW-TFTs) were fabricated and the mechanism for electrical conductance was studied.
Our results indicate that DG NW-TFTs have better electrical performance over SG NW-TFTs, including higher ON current, larger ON/OFF current ratio, steeper subthreshold slope(S.S.) and lower minimum drain current. Our results also show that stronger gate controllability that effectively suppresses the DIBL effect and lowers the leakage current in subthreshold region is achievable by employing the doubled-gated structure. In addition, the resultant DG device can act as a functional device by applying independent biases to two gates simultaneously, thus allowing the flexibility to adjust the threshold voltage of the device.
The single-gated nanowire TFT with high-k passivation was also discussed in this study. The Id-Vg characteristics show that the fringing field effect from the high-k passivation layer can effectively improve the device performance, including steeper
subthreshold slope, lower DIBL effect….etc.
In this study, we also found that both NH3 and N2 plasma treatments can dramatically improve the electrical performance of nanowire devices. In addition, we also found that the treatment time needed for suitable performance improvement is shorter with N2 plasma treatment.
6.2 Future works
In this thesis, we have explored various structural parameters of nanowire TFTs, such as single-gate, double-gate, gate oxide thickness, channel size, and passivation layer on the device performance.
In order to further improve the device performance, the following works are suggested for future research:
1. Several papers showed that the crystallization methods like SPC, MILC, ELC can effectively improve poly-Si channel quality. In this thesis, we concentrated our efforts on the SPC method. Other methods, such as MILC and ELC can be tried to improve the channel quality of DG NW-TFT in the future.
2. High-k gate dielectric is attractive for high performance devices. It could reduce the EOT while maintaining a higher physical thickness, thus lowering the leakage current. In addition, TFTs with high-k gate dielectric can have higher driving current. We can replace SiO2 gate dielectric with high-k material to improve device performance in the future.
3. The off-state leakage current associated with GIDL originated from the lightly-doped gate/drain overlapped region is still an important issue in our device. In the future, we can add an additional SiN layer between the main gate and drain to lower the electrical field, therefore alleviating the GIDL off-state leakage current.
4. The plasma passivation mechanism on nanowire device warrants further discussion. In the future, physical and chemical analyses such as SIMS,ECSA,OES…. can be employed to study the detailed mechanism.
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Table 3-1. Performance comparisons SG NW-TFTs and DG NW-TFTs (at V
D=0.5V
)V
th(V)
SS (mV/dec)
I
on(μA)
I
off(pA)
SG NW-TFTS 1.05 360 0.65 5.89
DG NW-TFTS 0.96 180 1.53 2.97
Table 3-2 Subthreshold slope for DG NW-TFTs (at V
D=0.5V) under various operation modes.
TG mode MG mode DG mode
DG1
( T
OX,topc=18nm) ( T
OX,main=18nm)
281 (mV/dec) 697 (mV/dec) 168 (mV/dec)
DG2
( T
OX,topc=60nm) ( T
OX,main=18nm)
733 (mV/dec) 496 (mV/dec) 205 (mV/dec)
Figure 2-1 (a) Schematics of double-gated nanowire thin-film-transistor.