Locations of PCB Components
Figure 2.2 depicts a sketch of PCB layout. Usually PCB board contains several kinds of components and connectors which are applied to specific interfaces. The length of signal net from package pin to component or connector on PCB is the primary contributor to parasitic inductance. Therefore, package pins will exacerbate simultaneous switching noise (SSN) by increasing the parasitic inductance in the signal nets [12]. The familiar equation shown below describes the basic mechanism of SSN (VSSN):
VSSN = NLtot(dI/dt) (2.1)
where N is the number of switching drivers, Ltot is the equivalent inductance in which current must pass through, and I is the current per driver. In order to minimize the physical length of the signal net and thus reduce the total parasitic inductance, package pins should be accommodated in particular regions. As shown in Figure 2.2, the minimum net-length can be obtained by assigning the order of pin-blocks according to the certain location of corresponding components or connectors then fine-tuning the direction of package properly.
Figure 2.2: A general layout of PCB board. The order of pin-blocks on IC package should be assigned according to the corresponding components then fine-tuned the direction of package to meet minimum net-length.
Routability
Another crucial factor of successful pin designation is routability. For routing issue, the inflexible package-board routing rules force the row number of signal pins, signal net width and spacing on PCB to be critical constraints. Figure 2.3 shows the simplified cross-section of a flip-chip package which is mounted on PCB board.
For a general 4-layer PCB board, only the top and bottom layers are allowed to be routed nets; the second and third layers are used for planning power/ground plane.
Based on the rules of thumb, package outer pins (solder balls located close to the package edge) connect solder bumps through vias and package top layer routing.
These outer pins are then inevitably routed on PCB top layer.
On the other hand, package inner pins located around the core of package must connect solder bumps by package bottom layer routing and then are routed on PCB bottom layer. Figure 2.4 demonstrates the routing pattern on PCB top layer and package bottom layer respectively. For instance, when the diameter of PCB pad is 14 mil (1 mil = 25.4 um), pad pitch is 39.37 mil, signal net width and spacing are both 5 mil on a 4-layer PCB board, the space between two pads can only be penetrated by two nets. It means only three rows of signal pins can be fanned out nets on PCB top layer. Because of these routing rules, the excess row number of signal pins will undoubtedly cause routing congestion due to restricted area between pins.
Figure 2.5 lists the confined row number of signal pins is constant and independent of the package sizes. In our example, the maximum row number of outer pins is nine and that of signal pins is seven (this happens when the nets on PCB bottom layer can be connected to four signal pins).
Signal Integrity
According to the routing pattern, shown in Figure 2.4, we can generalize the rule of thumb in assigning pins. That is, if signal pins are allocated on the same row,
Figure 2.3: Simplified cross-section of a flip-chip package mounted on PCB board.
Figure 2.4: The routing pattern on PCB top layer (a)(b) and package bottom layer (c)(d). Because of the routing rules and restricted area between pins, the confined row number of signal pins is six. The excess row number of signal pins will cause routing congestion during the package substrate and PCB routing phase.
Figure 2.5: The restricted row number of signal-pin is constant and independent of package size due to inflexible package-board routing rules (PCB pad=14 mil, pad pitch=39.37 mil, net width=5 mil, net spacing = 5 mil, for four layer PCB board).
their nets can have balanced routing, which means these nets will have matched impedance on PCB and package layout. On the other hand, if signal pins are allo-cated on the same column, only some nets can have balanced routing. The matched impedance is an essential requirement for high-speed differential systems, because it can eliminate the common mode noise thus improve the signal performance. For sig-nal integrity reason, return path inductance is another main course. The unsuitable placement and number of return path pins, which are power or ground pins, will maximize current return loops and increase return path inductance. This will dra-matically degrade signal integrity and exacerbate radiated emissions. Its mechanism is similar to that of SSN and has been shown in equation (2.1).
With regard to crosstalk noise, one of the major root causes is mutual capac-itance [12], mainly because it will inject a current onto the neighbor victim pins.
The induced noise (Inoise,Cm) is proportional to the mutual capacitance (Cm) and the rate in change of voltage on driven pins (dVdriver/dt):
Inoise,Cm = Cm(dVdriver/dt) (2.2)
Therefore, the optimal pin designation is to place signal pin and power/ground pin proximally close to each other, so that each signal pin can be tightly coupled to
a return path pin. This will minimize the effect of the return path inductance.
Furthermore, if signal pins surrounded with ground pins, the mutual capacitance will be decreased and the noise is shielded extremely. In [13, 14, 15], the effects of shielding, return path and reference plane are considered in package and PCB designs. However, those optimized designs, in terms of signal integrity concern, will create signal-pin blocks which have more power/ground pins but fewer signal pins within a large block area. The feasible designs of pin pattern are proposed in the next subsection.