We list some of possible future works as follows.
• Pin-out Designation Considering Ordered Escape Routing: The PCB routing problem has become increasingly difficult and no automated commer-cial tool can deal with high-end board routing very well [37]. As a result, routing task for high-speed PCB should be seriously confronted with. In gen-eral, such kind of routing problem can be divided into two categories, one is escape routing which routes nets from pin terminal (ball) to component boundaries, and another is area routing which routes nets between component boundaries [38]. For area routing, the planar bus routing fashion is always preferred to control and match impedance on each high-speed signal. One ap-proach regarding automatic bus planner for PCB was published very recently in [39]. On testing a state-of-the-art industrial circuit board, their bus plan-ner achieves 98.5% routing completion while simultaneously assigning routing layer and routing nets. However, the basic requirement of this bus planner is ordered escape routing which routing nets from balls to component bound-aries with a given order. Without ordered escape routing, no way can ensure that the planar bus routing between components can be done [40]. Therefore, our future work will aim at proposing a pin-out designation methodology con-sidering ordered escape routing. As shown in Figure 5.1, besides the signal integrity, power delivery integrity and routability we have already taken into account, we should strictly follow the given order and reduce escape routing layer at the same time while assigning pin-out.
Figure 5.1: The ordered escape routing (a)(b) and disordered escape routing (c)(d).
Our future work will follow the given order and reduce escape routing layer simul-taneously while designating pin-out.
• Chip-Package-Board co-simulated and co-optimized methodologies:
In designing high-speed electronic systems, more attention should be paid on interconnection between chip, package and board, it is because parasitics, in-terconnect attenuation and noise degrade signal quality on and off the chip thus limiting the system performance [41]. To enhance design’s robustness, another future work focuses on the co-simulation and co-optimization of system inter-connects after I/O-bump planning and pin-out designation. Figure 5.2 shows the expected design flow of our future work. To establish system’s wide-band model for co-simulation, we firstly extract the net parasitics from package and PCB routing results, then create wide-band lossy transmission line model for interconnects [42] [43]. Since the impedance-controlled interconnects play
Figure 5.2: The expected design flow of our future work at chip-package-board co-simulation and co-optimization.
a critical role in high-speed off-chip communications, they should be care-fully designed in order to avoid signal integrity problems such as reflection, overshoot, undershoot, and ringing [44]. Next, we want to accomplish the co-optimization tasks with impedance control and performance compensation.
Such tasks will refine interconnect and add passive devices such as de-coupling capacitor and termination resistor [45].
Bibliography
[1] A. Hasan and D. Sato, “BGA Package Ball Field Interaction with Manu-facturing and Design,” In Proceedings IEEE Electronic Componenets and Technology Conference, pp. 326-333, 2004.
[2] A.H. Titus and B. Jaiswal, “A Visualization-Based Approach for Bump-Pad/IO-Ball Placement and Routing in Flip-Chip/BGA Technology,” In IEEE Transactions on Advanced Packaging, vol. 29, no. 3, pp. 576-586, Aug.
2006.
[3] K. Sheth, E. Sarto and J. McGrath, “The Importance of Adopting a Package-Aware Chip Design Flow,” In Proceedings ACM/IEEE Design Automation Conference, pp. 853-856, 2006.
[4] A. Fontanelli, S. Arrigoni, D. Raccagni and M. Rosin, “System-on-Chip (SoC) Requires IC and Package Co-Design and Co-Verification,” In Proceed-ings IEEE Custom Integrated Circuits Conference, pp. 319-322, 2002.
[5] J. Mcgrath, “Chip/Package Co-Design: The bridge between chips and systems,” In Advanced Packaging Magazine, Jun. 2001 [Online]. Available:
http://ap.pennnet.com/display article/103319/36/ARTCL/none/none/1/
Chip/package-co-design/
[6] H.-M. Chen, I-M. Liu, D.-F. Wong, M. Shao and L.-D. Huang, “I/O Cluster-ing in Design Cost and Performance Optimization for Flip-Chip Design,” In
Proceedings IEEE International Conference on Computer Design, pp. 562-567, 2004.
[7] J. Xiong, Y.-C. Wong, E. Sarto and L. He, “Constraint Driven I/O Planning and Placement for Chip-package Co-design,” In Proceedings Asia and South Pacific Design Automation Conference, pp. 207-212, 2006.
[8] T.-O. Chong, S.-H. Ong, T.-G. Yew, C.-Y. Chung and R. Sankman, “Low Cost Flip Chip Package Design Concepts for High Density I/O,” In Proceed-ings IEEE Electronic Componenets and Technology Conference, pp. 1140-1143, 2001.
[9] M.-F. Yu and W. W.-M. Dai, “Single-Layer Fanout Routing and Routability Analysis for Ball Grid Arrays,” In Proceedings IEEE/ACM International Conference on Computer-Aided Design, pp. 581-586, 1995.
[10] S.-S. Chen, W.-D. Tseng, J.-T. Yan and S.-J. Chen, “Printed Circuit Board Routing and Package Layout Codesign,” In Proceedings IEEE Asia-Pacific Conference on Circuits and Systems, pp. 155-158, 2002.
[11] H.N. Brady, “An Approach to Topological Pin Assignment,” In IEEE Trans-actions on Computer-Aided Design of Integrated Circuits and Systems, vol.
3, no. 7, pp. 250-255, Jul. 1984.
[12] S.H. Hall, G.W. Hall and J.A. McCall, High-Speed Digital System Design.
New York: Wiley-Interscience Publication, 2000.
[13] N. Oka, C. Miyazaki, T. Uchida and S. Nitta, “Effect of a Shielding Plane Connected to Ground Plane of a PCB in EMI Reduction,” In Proceedings In-ternational Symposium on Electromagnetic Compatibility, pp. 204-207, 1999.
[14] T. Sudo, Y. Ko, S. Sakaguchi and T. Tokumaru, “Electromagnetic Radia-tion and Simultaneous Switching Noise in a CMOS Device Packaging,” In
Proceedings IEEE Electronic Componenets and Technology Conference, pp.
781-785, 2000.
[15] E. Diaz-Alvarez and J.P. Krusius, “Design, Simulation, Fabrication, and Characterization of Package-Level Micro-Shielding for EMI/EMC Manage-ment in BGA EnvironManage-ment,” In Proceedings IEEE Electronic Componenets and Technology Conference, pp. 793-798, 2000.
[16] Altera Corp., “Designing with High-Density BGA Packages for Altera De-vices,” Appl. Note AN-114-4.0, Feb. 2006.
[17] R. Vanderbei, “LOQO: An interior point code for quadratic programming,”
Technical report, Princeton University, Princeton, NJ, 1998.
[18] F.-Y. Young and D.-F. Wong, “Slicing Floorplans with Pre-Placed Mod-ules,” In Proceedings IEEE/ACM International Conference on Computer-Aided Design, pp. 252-258, 1998.
[19] F.-Y. Young, D.-F. Wong and H.-H. Yang, “Slicing Floorplans with Bound-ary Constraints,” In IEEE Transactions on Computer-Aided Design of In-tegrated Circuits and Systems, vol. 18, no. 9, pp. 1385-1389, Sep. 1999.
[20] F.-Y. Young, D.-F. Wong and H.-H. Yang, “Slicing Floorplans with Range Constraint,” In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 2, pp. 272-278, Feb. 2000.
[21] Y.-H. Jiang, J. Lai and T.-C. Wang, “Module Placement with Pre-Placed Modules Using the B*-Tree Representation,” In Proceedings Internationl Symposium on Circuits and Systems, pp. 347-350, 2001.
[22] J.-M. Lin, H.-E. Yi and Y.-W. Chang, “Module Placement with Bound-ary Constraints Using B*-trees,” In IEE Proceedings–Circuits, Devices and Systems, pp. 251-256, 2002.
[23] H. Murata, K. Fujiyoushi, S. Nakatake and Y. Kajitani, “Rectangle-Packing-Based Module Placement,” In Proceedings IEEE/ACM International Con-ference on Computer-Aided Design, pp. 472-479, 1995.
[24] Y.-C. Chang, Y.-W. Chang, G.-M. Wu and S.-W. Wu, “B*-Trees: A New Representation for Non-Slicing Floorplans,” In Proceedings ACM/IEEE De-sign Automation Conference, pp. 458-463, 2000.
[25] A. E. Caldwell, A. B. Kahng, S. Mantik and I. L. Markov, “Implications of Area-Array I/O for Row-Based Placement Methodology,” In Proceedings IEEE Symposium on IC/Package Design Integration, pp. 93-98, 1998.
[26] J. Wang, K. K. Muchherla and J. G. Kumar, “A Clustering Based Area I/O Planning for Flip-Chip Technology,” In Proceedings International Sym-posium on Quality Electronic Design, pp. 196-201, 2004.
[27] G. Pascariu, P. Cronin and D. Crowley, “Next Generation Electronics Pack-aging Utilizing Flip Chip Technology,” In IEEE International Electronics Manufacturing Technology Symposium, pp. 423-426, 2003.
[28] C.-Y. Chang and H.-M. Chen, “Design Migration From Peripheral ASIC Design to Area-I/O Flip-Chip Design by Chip I/O Planning and Legaliza-tion,” In IEEE Transactions on Very Large Scale Integration Systems, vol.
16, no. 1, pp. 108-112, Jan. 2008.
[29] C. Tan, D. Bouldin and P. Dehkordi, “Design Implementation of Intrin-sic Area Array ICs,” In Proceedings Seventeenth Conference on Advanced Research in VLSI, pp. 82-93, 1997.
[30] V. Maheshwari, J. Darnauer, J. Ramirez and W. W.-M. Dai, “Design of FP-GAs with Area I/O for Field Programmable MCM,” In Proceedings ACM In-ternational Symposium on Field-programmable gate arrays, pp. 17-23, 1995.
[31] J.-W. Fang, I.-J. Lin, Y.-W. Chang and J.-H. Wang, “A Network-Flow Based RDL Routing Algorithms for Flip-Chip Design,” In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 8, pp. 1417-1429, Aug. 2007.
[32] J.-W. Fang, C.-H. Hsu and Y.-W. Chang, “An Integer-Linear-Programming-Based Routing Algorithm for Flip-Chip Designs,” In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 1, pp. 98-110, Jan. 2009.
[33] H.-M. Chen, I-M. Liu and D.-F. Wong, “I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design,” In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 11, pp. 2552-2556, Nov. 2006.
[34] J.-W. Fang and Y.-W. Chang, “Area-I/O Flip-Chip Routing for Chip-Package Co-Design,” In Proceedings IEEE/ACM International Conference on Computer-Aided Design, pp. 518-522, 2008.
[35] J. Desai and Y. Rao, “Avoid Design Issues with Package-Aware I/O Planning,” In EE Times India, Oct. 2008 [Online]. Available:
http://www.eetindia.co.in/ART 8800546925 1800000 NT 2f421812.HTM [36] T. Meister, J. Lienig and G. Thomke, “Novel Pin Assignment Algorithms
for Components with Very High Pin Counts,” In Proceedings Design, Au-tomation and Test in Europe, pp. 837-842, 2008.
[37] H. Kong, T. Yan, D.-F. Wong and M. M. Ozdal, “Optimal Bus Sequencing for Escape Routing in Dense PCBs,” In Proceedings IEEE/ACM Interna-tional Conference on Computer-Aided Design, pp. 390-395, 2007.
[38] M. M. Ozdal and D.-F. Wong, “Algorithms for Simultaneous Escape Routing and Layer Assignment of Dense PCBs,” In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 8, pp. 1510-1522, Aug. 2006.
[39] H. Kong, T. Yan and D.-F. Wong, “Automatic Bus Planner for Dense PCBs,” In Proceedings ACM/IEEE Design Automation Conference, pp. 326-331, 2009.
[40] L. Luo and D.-F. Wong, “Ordered Escape Routing Based on Boolean Sat-isfiability,” In Proceedings Asia and South Pacific Design Automation Con-ference, pp. 244-249, 2008.
[41] M. Shen, L.-R. Zheng and H. Tenhunen, “Robustness Enhancement Through Chip-Package Co-Design for High-Speed Electronics,” In Proceedings Inter-national Symposium on Quality Electronic Design, pp. 184-189, 2004.
[42] A. Deutsch, P. W. Coteus, G. V. Kopcsay, H. H. Smith, C. W. Surovic, B. L. Krauter, D. C. Edelstein and P. J. Restle, “On-Chip Wiring Design Challenges for Gigahertz Operation,” In Proceeding of the IEEE, vol. 89, no.
4, pp. 529-555, Apr. 2001.
[43] C. S. Yen, Z. Fazarinc, and R. L. Wheeler, “Time-Domain Skin-Effect Model for Transient Analysis of Lossy Transmission Line,” In Proceeding of the IEEE, vol. 70, no.7, pp. 750-757, Jul. 1982.
[44] B. Young, Digital Signal Integrity: Modeling and Simulation with Intercon-nects and Packages, Prentice Hall PTR, 2001.
[45] T. J. Gabara and S. C. Knauer, “Digitally Adjustable Resistors in CMOS for High-Performance Applications,” In IEEE Journal of Solid-State Circuits, vol. 27, no. 8, pp. 1176-1185, Aug. 1992.
Vita
• Personal Information:
– Name: Ren-Jie Lee
– Date of Birth: 1972/09/23 – Sex: Male
– Permanent Address: No.120-9, Guandong, Gongguan Township, Miaoli County 363, Taiwan (R.O.C.)
– Permanent Phone: 886-37-224953
– Email: [email protected]; [email protected]
• Education: (School; Degree; Majors [Research Topics]; Period; Status)
– Feng Chia University; Master; Electronics Engineering [RFIC design];
1998/09/01∼2000/06/23; Graduate
– National Chiao Tung University; Ph.D.; Electronics Engineering [EDA];
2006/09/01∼2010/02/25; Graduate
• Employment History: (Position; Period; Company; Address)
– Project Manager; 2000/06/26∼2006/07/31; Silicon Integrated System (SiS) Corp.; NO. 180, Sec. 2, Gongdaowu Rd., Hsinchu City 300, Taiwan (R.O.C.)
• Research Collaboration Experience: (Project; Period; Collaborator;
Affiliation)
– PCB planar router development; 2007/07/01∼ ; Prof. Yoji Kajitani;
Department of Information and Media Engineering, The University of Kitakyushu, Kyushu, Japan
– Touch Pad Sensor Modeling and Analysis; 2008/06/01∼2009/10/31;
R&D Director, Vincent Tao; Product Development Division, ELAN Microelectronics Corp., Hsinchu Science Park, Hsinchu City 300, Taiwan (R.O.C.)
• Specialties and Skills:
– SoC designs implementation flow – Package and PCB design and planning – C/C++ programming
– Outstanding Employee Award, Silicon Integrated System (SiS) Corp., 2005.
– Pre-PhD Teaching Assistant Scholarship, National Chiao Tung Univ., Fall, 2006.
– Outstanding Teaching Assistant Award, National Chiao Tung Univ., Spring, 2007.
– Pre-PhD Teaching Assistant Scholarship, National Chiao Tung Univ., Fall, 2007.
– Outstanding Teaching Assistant Award, National Chiao Tung Univ., Spring, 2008.
Publication List
1. R.-J. Lee and H.-M. Chen, “Fast Flip-Chip Pin-Out Designation Respin for Package-Board Codesign,” In IEEE Transactions on Very Large Scale
Integration Systems (TVLSI), vol. 17, no. 8, pp. 1087-1098, Aug. 2009.
2. R.-J. Lee and H.-M. Chen, “Efficient Package Pin-Out Planning with System Interconnects Optimization for Package-Board Codesign,” to appear, IEEE Transactions on Very Large Scale Integration Systems (TVLSI).
3. R.-J. Lee, M.-F. Lai and H.-M. Chen, “Fast Flip-Chip Pin-Out Designation by Pin-Block Design and Floorplanning for Package-Board Codesign,” In Proceedings IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 804-809, 2007.
4. R.-J. Lee, C.-L. Weng and H.-M. Chen, “Wirelength-Driven Flip-Chip Pin-Out Designation by Range Constrained Pin-Block Planning in
PCB-Package Codesign,” In 19th VLSI Design/CAD Symposium, Kenting, Taiwan, 2008.
5. R.-J. Lee and H.-M. Chen, “Design Planning for Chip-Package-Board Co-Design,” In 12th SIGDA Ph.D. Forum at ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, 2009.
6. R.-J. Lee and H.-M. Chen, “Efficient Package Pin-Out Planning with Chip-Package Interconnects Optimization,” In Proceedings IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS), Hong Kong, China, 2009.
7. R.-J. Lee and H.-M. Chen, “Novel I/O-Bump Design and Optimization for Chip-Package Codesign,” In Proceedings IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS), Hong Kong, China, 2009.