CoolMOS

CoolMOS is a novel power MOSFET with a “superjunction” for its drift region, which results in a vastly improved relationship between the on-resistance and breakdown voltage [20].

Power MOSFETs are commonly used as switches in power electronic circuits, and they should have minimal resistance when the device is conducting and sustain high voltage when it is off. For a higher breakdown voltage, power MOSFETs are usually fabricated as a vertical double-diffused structure with a lightly doped epitaxial drift layer to sustain the voltage. The breakdown voltage (VB) of the device is

increased by reducing the doping concentration and increasing the thickness of the drift layer. However, this results in an increase of the on-resistance (Ron). It can be shown that Ron is proportional to VB2.5

[21], which means that increasing VB will result in a significant increase in Ron, causing higher conduction losses. The CoolMOS is evolved from a conventional DMOS structure but it breaks the more than square law dependence in the case of standard DMOS with the linear voltage relationship in specific on-resistance. CoolMOS is a novel power MOSFET projected as the latest milestone in high-voltage MOSFET devices. In the CoolMOS, the drift region of the conventional DMOS is replaced by a “superjunction”—a combination of n^- and p^- strips in parallel (Fig. 1.3).

When the device is on, the n^- strip conducts the drain current. When it is off, a drain voltage (VD) is applied, and it appear as a reverse bias between the n^- and p^- strips. A depletion region forms, and a relatively small value of VD fully depletes the drift layer. Subsequently, the behavior of the drift region is similar to that of an intrinsic layer. For an example, based on the new device concept of charge compensation the Ron area product of 600 V transistor has been reduced by a factor of 5 [22].

CoolMOS shows no bipolar current contribution like the well known tail current observed during the off-state of the IGBTs. CoolMOS virtually combines the low switching losses of a MOSFET with the on-state losses of an IGBT. Moreover, while the donor and acceptor charge reach the balance state in their depletion regions, the superior

MOSFETs. Additionally, it also can be attempted to develop lateral superjunction structure into silicon-on-insulator (SOI) to increase their voltage blocking capability (Fig. 1.4) [23].

Chapter 2

Device Physics of the CoolMOS

2.1 CoolMOS in the Off-State

The behavior of the CoolMOS transistor in the off state is dominated by the characteristics of the superjunction drift layer. Here, first explain, with the help of simulation results, why the breakdown voltage is higher in the superjunction structure. We will then discuss how the doping density of the n^－ and p^－ strips can be chosen to achieve the minimum on resistance.

To understand how the superjunction drift layer improves the breakdown voltage in the CoolMOS transistor, the superjunction (SJ) is simulated here alone (i.e., without the MOS structure) and compare it with the drift region of a conventional power MOSFET, which is simply a lightly doped (LD) layer without any p-n junction. Fig. 2.1 shows the two simulated structures. The n^＋ and p^＋ contact regions are heavily doped (Nd=Na=3×10¹⁹cm^-3), the n^－ and p^－ strips, and the n^－ layer of the LD structure are lightly doped (Nd=Na=3×10¹⁵cm^-3). The p⁺ contact is grounded, and a positive voltage is applied to the n⁺ contact. The superjunction structure was found to break down at 300 V, while the LD

structure could sustain only 130 V [24].

In Fig. 2.2, we have plotted the electric field for the LD structure. As this is effectively a one-dimensional (1-D) structure, there is no variation in the x direction. In Fig. 2.3, the net electric field for the SJ structure along the outer edge of the n^－ strip is plotted. This field is also vertical because of symmetry. For the LD structure, the field profile is triangular, with constant slope, and advancing toward the n^＋ contact, as the applied voltage increases. Note that, in this structure, the depletion region expands gradually as the voltage increases. For the SJ structure, on the other hand, the n^－ and p^－ strips become completely depleted (which is indicated by the field becoming nonzero) at a relatively low voltage, about 50 V for this example. The field profile for larger voltages retains its relatively flat shape, with steep variations only near the contacts.

The following two observations, along with the field profiles, will explain the superior VB of the SJ structure: (i) The voltage difference between the contacts in both LD and SJ structures is simply the area under the field profiles plotted in Fig. 2.2 and 2.3. This is because the electric field is vertical in both the structures, as that has pointed out. (ii) For the SJ structure, the field is maximum at the junctions along the two edges (and these two values are equal in our device because of symmetry) [25]. Thus, in each of the two structures, LD and SJ, the breakdown voltage is simply the area under the field profile when the maximum field reaches a critical value. Now, looking at the shape of the field profiles, it is easy to see that VB will always be higher for the SJ structure than that for the LD structure, because the area is larger in the SJ case.

When the height of the superjunction region was increased from 15 μm to 25μm, without changing any other parameter, VB increased from 300 to 500 V. The field profiles at breakdown for the SJ structure for these two heights are seen to coincide almost exactly for 15μm (Fig. 2.4).

Since Ron has also increased in the same proportion as the height of the SJ region, the linear relationship between Ron and VB for the SJ structure has been proved by this result.

2.2 CoolMOS in the On-State

The on-resistance of the conventional high voltage Power MOSFET is dominated by the resistance of the voltage sustaining drift layer. The blocking capability of this region is determined by its thickness and the doping [26] [27]. In order to increase the blocking voltage the doping must be simultaneously reduced and the layer thickness increased. The resistance of the transistor therefore increases disproportionately strongly as a function of its blocking capability. Accordingly the drift layer causes over 95% of the total on-resistance in e.g. a 600V transistor [28]. The main emphasis in improving the transistors performance must therefore be directed towards reducing this drift region resistance.

CoolMOS in the on state, electrons flow from the source, under the gate electrode (i.e., through the MOSFET channel), through the drift region (i.e., the n^－ part of the superjunction), to the drain terminal (Fig.

2.5). We can therefore consider the device to be made up of an “intrinsic”

MOSFET and a drift region. We have simulated the device in the on state, by applying a positive bias to the gate. The transfer characteristics are similar to those of a conventional power MOSFET. The device turns on at the threshold voltage of the “intrinsic” MOSFET, and the current rises with VG initially and saturates when the resistance of the drift region starts dominating. The characteristics saturate after a small increase in VG

(less than 1 V) in the simulated device, indicating a high drift region resistance, as compared to that of the intrinsic MOSFET.

The ID–VD characteristics show two distinct regimes (Fig. 2.6). For lower values of VG, saturation in the conventional sense is observed; i.e., as VD becomes high, the intrinsic MOSFET saturates. For higher values of VG, the current does not saturate completely, but undergoes a “partial”

saturation and rises slowly with VD. It is also seen that, in this region, there is hardly any increase in the current with increasing VG (between VG = 10 V and 30 V). This implies that some mechanism other than the usual MOSFET saturation must be responsible for this “quasi” saturation of current at large gate voltages. The quasi-saturation was thought to be due to degradation of mobility, as the electric field increases [29] [30]. To test the validity of this conjecture, the device was simulated with a constant mobility, and it was found that saturation indeed ceases to occur in this condition. This confirms that quasi-saturation is related to mobility degradation. We can conclude from some study that at higher gate voltages, saturation of the ID–VD curve occurs due to velocity saturation in the drift region, first in the neck region, and then, at higher drain voltages, also in the pillar region. When quasi-saturation occurs, the

depletion region stops advancing further into the n^－ region and the electron density in the n^－ regions increases slightly above its equilibrium value.

The situation at lower gate voltages (e.g., VG = 7.5 V for the simulated structure) is different. The saturation of the ID–VD curve in this case is caused by the usual saturation of the intrinsic MOSFET. When VD

was made more than 50 V, however, we observed that velocity saturation occurred in the drift region. As the intrinsic MOSFET is in saturation, this does not reflect on the ID–VD curve.

2.3 Analyses of the Drift pillar, the Current, and the Specific On-Resistance

The “pillar” portion of the n^－ drift region of the CoolMOS transistor is not present in conventional power MOSFETs, as we pointed out previously. Analytical modeling of this region was therefore undertaken, considering it to be equivalent to the JFET-type structure shown in Fig.

2.7, as suggested by the observed depletion region behavior. The gate, source, and drain terminals are defined for this JFET as shown in Fig. 2.7.

Using the depletion approximation, we can write, assuming Na = Nd = N ω(y) = (εsiVG/qN)^1/2 (1) The total current at a given y is

I = -zh(y)/ρ‧dV/dy (2) Where h(y) = cp/2 -ω(y) ( cp/2 being the width of the n^－ pillar Wn) can be shown to be

h(y) = cp/2 [1 – (V(y) - VG / Vp)^1/2] (3) Vp in Eq. (3) is the pinch-off voltage Vp = q‧(cp/2)²‧N / εsi. Now, integrating over the length of the structure, the current can be obtained as

I = G0‧V_p[VDS / Vp + 2/3(-VGS / Vp)^3/2 – 2/3(VD – VG / Vp)^3/2] (4) with G0 = cp‧z / 2ρ‧tepi. It can be seen that (4) is similar to that for a conventional JFET [24].

For the device to block maximum voltage, the charge (Q) in the n^－ and p^－ pillars should be exactly balanced and chosen such that the pillars are compietely depleted before breakdown (i.e. Q < εsiEC / q). This ensures that the electric field profile is flat (and not triangular as in the standard MOSFET case) and the breakdown is dependent just on the epilayer thickness and independent of the doping concentration.

Assuming a perfectly flat electric field profiIe and Wn = Wp = cp/2, the VB and Q are given by

VB = EC‧t_epi (5) Q = Nd‧cp / 2 =ε_si‧E_C / q (6) where EC, is the critical electric field strength, tepi is the thickness of the epitaxial layer (height of the pillars), Nd is the doping concentration of the n^－ pillar and cp is the cell pitch. Using (5) and (6) in the Ron equation

Ron = tepi / qμnNd (7) leads to

Ron = cp‧VB / 2qμ_nECQ = cp‧VB / 2μ_nε_si EC

2 (8) Equation (8) clearly shows that the relation between the VB and Ron of the CoolMOS is linear, unlike the power law relationship

Ron = 6‧10^-9VB

2.5 (9) of the conventional DMOS device, thereby giving the CoolMOS a huge advantage over conventional MOSFETs. Equation (8) also points out that Ron is inversely proportional to Q and hence Q should be kept as high as passible to get the lowest on-resistance. It may also be noted that Ron of the CoolMOS is directly proportional to the cell pitch and hence it is extremely important to make the tall pillars as narrow as possible [31]-[34].

Chapter 3 Simulation Process

3.1 Simulation Software

Several software packages are available to arrive at a realistic and satisfactory simulation. Integrated Systems Engineering Technology Computer Aided Design (ISE-TACD) tools is one such package (Fig. 3.1).

This software comprises several modules, such as MESH-ISE for grid generation, DESSIS-ISE for device and circuit simulation, FLOOPS-ISE for process simulation, MDRAW-ISE, one structure and mesh information display, and visualization tools like INSPECT and TECPLOT-ISE.

In the simulation package ISE-TCAD, the basic semiconductor equations (e.g. Poisson’s and electron-hole continuity equations) are numerically solved on the mesh points mapped over the device structure.

The numerical solution converges in accordance with the defined criteria for analysis. The typical input consists of structure of the device, mesh size, impurity profiles in different regions, and physical effects and models for performing the simulation. The input is given in the form of files, the mesh boundary file for defining the geometry of the device under examination; the mesh command file for impurity profiles in the structure and mesh refinements to focus at the critical regions of the

device; and the dessis command file for specifying the voltages and currents applied on the electrodes of the device, physical models to be used in the simulations, the permissible errors in the parameters, the number of iterations to be done, and the method of solving Poisson’s equation, along with the approach to problem solving, whether transient, quasi-stationary, and so on. “Quasi-stationary command” is used to ramp a device from one solution to another by modifying its boundary conditions (e.g. ramping of the voltage at an electrode). “Transient command” is used to run a transient solution.

On the other words, we utilize FLOOPS-ISE to simulate the process, and MDRAW-ISE to produce the mesh of the device. DESSIS-ISE is used to result the behaviors of the device at several conditions. After that, INSPECT tool can show voltages and currents curves, and TECPLOT-ISE is utilized to display electric field, electric potential, current density distribution, etc.

3.2 Super-Junction Structure Simulation

First, we utilize FLOOPS to simulate the process of the SJ structure. Process flow and condition are defined as:

(a) Set up the substrate with n-type (100)-oriented silicon wafer ( Nd=3×10¹⁹cm^-3 ).

(b) Grow epitaxial layer 0.25 μ m with doping phosphorous ( Nd = 3×10¹⁵ cm^-3 ).

(c) Annealing 15 second at 550 ℃.

(d) Etch the left-half of the epi-layer.

(e) Utilize selective growth to fill the left-half with doping boron epitaxion ( Na=3×10¹⁵ cm^-3 ).

(f) Annealing 15 second at 550 ℃.

(g) Repeat (b)~(f) 60 times to achieve a 15 μm pillar.

(h) Deposit a 3 μm layer with doping boron ( N a=3×10¹⁹ cm^-3 ) as upper side.

(i) Contact upper and lower electrode.

And then, we put the structure (Fig. 3.2) into DESSIS-ISE to simulate its electrical properties. Here, we set up the across voltage from 10 V to 300 V.

3.3 The Simulation of the Complete Structure of the CoolMOS

By observing the SJ structure simulation, we can confirm that our device simulation is practicable. Then, we will proceed to accomplish the CoolMOS structure complete:

(A) Continuing using previous flow for SJ structure simulation, we let the pillar grows to 20μm - namely repeat (b)~(f) 80 times.

(B) Etch a 3 μm trench for p-base.

(C) Fill the trench with doping boron deposition (N a=5.5×10¹⁶cm^-3).

(D) Use implantation to define the source region (N d=3×10¹⁹cm^-3).

(E) Grow a 0.1μm oxidation layer for gate oxide.

(F) Contact the source, gate, and drain electrodes.

Fig. 3.3 shows the complete structure, and we could find that the tools spread impurities diffusion out distinct. Furthermore, during simulation process, we pay attention on impact ionization effect. Namely, avalanche breakdown function has been pondered over. At next section, we will list all simulative conditions in detail.

3.4 Simulative Conditions in Detail

From reference papers, we know that the drift region (the pillar) controls the greater part characteristics of the device. Above all, we take a focus on the doping concentration of the region.

In the first instance, we dominate the concentrations at n- and p- region equilibrium, and set up three different values to observe the influences:

N a = N d = 3 × 10¹⁵, 6 × 10¹⁵ , 9 × 10¹⁵ cm^-3

Having fabrication element in mind, we deliberately let the

concentrations imbalance with the standard condition of N a = 6 × 10¹⁵ cm^-3:

(1) n^- region raises up 5 % and 10 % to N d = 6.3 × 10¹⁵ and 6.6

× 10¹⁵ cm^-3 ;

(2) n^- region cuts down 5 % and 10 % to N d = 5.7 × 10¹⁵ and 5.4 × 10¹⁵ cm^-3 ;

And then, we discuss the cases of N a ≠ N _d . By the same way, letting N a = 6 × 10¹⁵ (cm^-3) to be the standard condition, we change that :

N d = 6 × 10¹⁴ , 3 × 10¹⁵ , 9 × 10¹⁵ , and 1.2 × 10¹⁶ cm^-3 .

Chapter 4

Results and Discussions

4.1 About the Super-Junction Structure

From Fig. 4.1, it shows the result that is similar to other studies.

When the pillar is not depleted completely, the electric field distribution of that is a triangular form. Otherwise, this shape is rectangle like. So, in the same length and critical electric field, this structure has higher breakdown voltage indeed. This result takes a good few confidence in the following simulation.

4.2 Doping Concentration inside the Pillar Region for Balance Condition

Under balance conditions, the electric field and electron density at off-state (Vg = 0) are shown in Fig. 4.2 ~ 4.4 for the doping concentration of 3 × 10¹⁵, 6 × 10¹⁵ and 9 × 10¹⁵ cm^-3 respectively, inside the pillar regions. The electron density curves indicate that it is more difficult to deplete completely as the doping concentration is heavier. Hence, higher voltage drop occurs at the neck region. Generally, heavier doping concentration easily reaches the critical electric field strength of the

material ( Ec ≒ 3 × 10⁵ V/cm for silicon ). As the decease in the pillar doping concentration, the electric field curve shows more flattening, and it can be manifested that the lighter doping pillar is capable of sustaining higher breakdown voltage.

As shown in Fig. 4.5, the driving force of current increases, and as everyone knows, the on-resistance decreases with the doping concentration increasing. As stated above, doping concentration should not be increased randomly. There is one optimal pillar doping concentration for choice within the safe operating area (SOA). In Fig. 4.6, the transfer characteristics are similar to those of a conventional power MOSFET. Although CoolMOS cannot improve the rapid saturation at low voltage level, it does not sway the good manifestation of the device at high voltage level.

Quasi-saturation is seen obviously at the Id-Vd curves (Fig. 4.7~4.9), and it is improved with concentration increasing. However, the Fig. 4.10 shows that there is an optimal pillar doping concentration to alleviate quasi-saturation effect. This result might occur by that the concentration is near the level of the p-base ( 5.5×10¹⁶ cm^-3).

Fig. 4.11 provides another view to probe the locations with breakdown occurrence. In the p-n junction, the peak value of the electric field strength always presents. Fig. 4.12 is a 2-D map of the electric field distribution, and it points apparently out that is not think so, this peak value is lower than the value at the neck region a lot. Perhaps it is necessary to take some focus on the p-n junction, we want to improve the problem of the breakdown voltage.

4.3 Comparison between General Saturation and Quasi-saturation

In the quasi-saturation state, the space charge distribution are presented in Fig. 4.13 with different drain voltages at Vg of 15 (V) for the pillar doping concentration of 9×10¹⁵ (cm^-3). The depletion region inside the n-pillar begins to advance the pillar center part as drain voltage increasing and then expands difficultly to the n pillar region. However, as the increasing of the drain voltage, the space charge gradually makes the p-pillar to be full depletion. The extra carrier density generated in the current path as shown in Fig. 4.14 can explant this phenomenon.

Fig. 4.15 and Fig. 4.16 show the variations of space charge and electric field within general saturation for the pillar doping concentration of 3×10¹⁵ (cm^-3). The depletion regions inside the n-pillar and p-pillar both expand uniformly with increasing of the drain voltage, and the current path is clipped from top to bottom. The electric field distributes in the p-n junction and the neck region uniform. Indeed, Fig. 4.17 shows the current path has no extra carrier density like that within quasi-saturation. By the same way, to observe the variation of space charge and electric field within quasi-saturation (Fig. 4.18, 4.19), not only the depletion region expands difficultly into the current path, but also that is clipped from bottom to top. The electric field density masses at the neck region and the bottom of the p-n junction.

Finally, taking a conclusion for the comparison between general-

and quasi-saturation, we let the drain voltage in the same level (Fig. 4.20).

The region under the gate, its potential is zero within quasi-saturation, but that is not within general saturation. This shows that the channel at p-base is pinched off just like an “intrinsic” MOSFET, when the device is at saturation. However, the large enough gate voltage causes an accumulation layer near the p-base channel, and this phenomenon makes the area between the region under the gate and the source region like a short circuit. The electron current directly flows from source to the top of the current path without decay, and then drifts towards the bottom of the device by drain voltage pulling in. So that, the quasi-saturation effect lets the device to be like a large resistance.

The region under the gate, its potential is zero within quasi-saturation, but that is not within general saturation. This shows that the channel at p-base is pinched off just like an “intrinsic” MOSFET, when the device is at saturation. However, the large enough gate voltage causes an accumulation layer near the p-base channel, and this phenomenon makes the area between the region under the gate and the source region like a short circuit. The electron current directly flows from source to the top of the current path without decay, and then drifts towards the bottom of the device by drain voltage pulling in. So that, the quasi-saturation effect lets the device to be like a large resistance.