Future Works

This study has successfully simulated the operating mode of CoolMOS by the working environment of ISE-TACD. Meanwhile, observations have been made on the distribution properties of space charge and electric field. Through these observations, it has been discovered that, at the time of quasi-saturation, accumulation layers appear near p-base below gate. This distinguishes apparently the electric properties of devices at the time of quasi-saturation from those at the time of general saturation. Imbalance of doping concentration also affects electric properties. Yet, a useful conclusion has been drawn from the examination of concentration imbalance. That is: quasi-saturation is closely correlated to the doping concentration of the n-pillar.

5.2 Future Works

Of course, mastering simulation software is the initial and fundamental step. In the future, thorough examination on CoolMOS by ISE-TACD will continue to be engaged. At present, one preliminary plan has been conceived. This plan involves including thermal effect and

various kinds of particle effects into the conditions of device simulation so that the simulative results obtained can approximate the reality to the greatest extent. This done, more precise observation of the breakdown mechanism can be undertaken. If the timing and location of breakdown occurrence can be precisely identified, device properties can be improved more efficiently, or even more advanced device structures can be developed.

And then, we will go deep into observing the quasi-saturation effect to find out its complete mechanism. High frequency operating mode might be one of the future works for us.

References:

[1] B. J. Baliga, “An overview of smart power technology”, IEEE Trans.

on Elec. Dev., vol. 38, pp. 1568-1575, 1991.

[2] V. Khemka, V. parthasarathy, R. Zhu, and A. Bose, “Correlation between static and dynamic SOA (energy capability) of RESURF LDMOS device in smart power technologies”, IEEE Proc. ISPSD, pp.

125-128, 2002.

[3] K. Ishiguri, M. Hoshino, A. Iwabuchi, and N. Aoike, “Power IC of electric ballast for automotive HID lamp”, IEEE Indust. Appl. Conf., vol. 5, pp. 3388-3393, 2000.

[4] A. Adahl, and H. Zirath, “An 1GHz class E LDMOS power amplifier”, Mircowave conf., vol. 1, pp. 285-288, 2003.

[5] T. Yue, M. Kumar, C. Jun, and J. K. O. Sin, “A SOI LDMOS technology compatible with CMOS, BJT, and passive components for fully-integrated RF power amplifiers”, IEEE Trans. on Elec. Dev., vol.

48, pp. 2428-2433, 2001.

[6] H. Sumida, A. Hirabayashi, H. Shimabukuro, Y. Takazawa, and Y.

Shigeta, “A high performance plasma display panel driver IC using SOI”, IEEE Proc. ISPSD, pp. 137-140, 1998.

[7] M. Tsuneoka, M. Takeuchi, and I. Takahashi, “The design of RF power supply using DC-CD converter”, IEEE Symp. on Fusion Eng., pp. 1206-1209, 1989.

[8] T. Letavic, M. Simpson, E. Arnold, E. Peters, R. Aquino, J. Curcio, S.

Herko, and S. Mukherjee, “600 V power conversion system-on-a-chip based on thin layer silicon-on-insulator”, IEEE Proc. ISPSD, pp.

325-328, 1999.

[9] M. Hack, A. Chiang, T. Y. Huang, A. G. Lewis, R. A. Martin, H. Tuan, I. W. Wu, and P. Yap, “High-voltage thin film transistor for large area microelectronics”, IEEE IEDM Tech. Dig., pp252-255, 1988.

[10] F. J. Clough, Y. Chen, E. M. S. Narayanan, W. Eccleston, W. I. Milne,

“A novel thin film transistor for high voltage circuit on glass”, IEEE Proc. ISPSD, pp. 321-324, 1997.

[11] S. Abedinpour, and K. Shenai, “Power electronic technology for the new millennium,” IEEE Int. Caracas Conf. On Devices, circuits, and Systems, pp. 111-1~111-9, 2000.

[12] M. Trivedi, and K. Shenai, “Performance of silicon carbide devices in power converter,” Int. Workshop Integrated Power Packaging, pp.

17-20, 2000.

[13] A. Abou, A. M. Radum, V. Arthur, R. H. Chang, and C. Winerhalter,

“A 1 MHz hard-switched silicon carbide DC/CD converter,” IEEE Applied Power Electronics Conf. and Exposition (APEC), vol. 1, pp.

132-138, 2003.

[14] I. Takahashi, “SiC power converter technology in future,” Int.

Electric Machines and Drives Conf. (IEMDC), vol. 3, pp. 1903-1908, 2003.

[15] R. Singh, D. C. Capell, M. K. Das, L. A. Lipkin, J. W. Palmour,

“Development of high-current 4H-SiC ACCUFET” Electron Devices, IEEE Transactions, 2003.

[16] B. J. Baliga, Power Semiconductor Devices. Boston, MA: PWS, 1996.

[17] B. J. Baliga, M. S. Adler, P. V. Gray, R. P. Love, and N. Zommer,

“The insulated gate rectifier,” in IEEE Int. Electron Devices Meeting, 1982, Abstract 10.6, pp. 264-267.

[18] M. Trivedi, and K. Shenai, “Evaluation of planar and trench IGBT for hard and soft switching performance,” IEEE IAS, pp. 717-721, 1999.

[19] Y. Onishi, S. Momota, Y. Kondo, M. Otsuki, N. Kumagai, and K.

Sakurai, “Analysis of device structures for next generation IGBT,”

IEEE Proc. ISPSD, pp. 85-88, 1998.

[20] L. Lorenz, G. Deboy, A. Knapp, and M. Marz, “COOLMOS-A new milestone in high voltage power MOS,” in IEEE Int. Symp.

PowerSemiconductor Devices and ICs, 1999, pp. 3–10.

[21] B. J. Baliga, Modern Power Devices. New York: Wiley, 1987.

[22] L. Lorenz, M. März, “CoolMOS^TM-a new approach towards high efficient power supplies,” PCIM Europe (6/1999).

[23] D. Shahrjerdi, M. Fathipour, B. Hekmatshoar, A. Khakifirooz, “A lateral structure for low-cost fabrication of COOLMOS^TM,”

Solid-State Electronics 48 (2004), pp. 1953-1957.

[24] B. J. Daniel, C. D. Parikh, and M. B. Patil, “Modeling of the CoolMOS^TM Transistor-Part I: Device Physic,” IEEE Tran. On Electron Devices, vol. 49, NO. 5, May 2002.

[25] T. Fujihira, “Theory of semiconductor superjunction devices,” Jpn. J.

Appl. Phys., vol. 36, p. 6254, 1997.

[26] B. J. Baliga,“Power semiconductor devices for variable frequency drives,” Proc. IEEE, vol. 82, pp. 1112–1122, 1994.

[27] T. Syau, P. Venkatraman, and B. J. Baliga, “Comparison of ultralow specific on-resistance UMOSFET structures,” IEEE Trans. Electron Devices, vol. 41, pp. 800–808, 1994^.

[28] L. Lorenz, G. Deboy, M. März, J.-P. Stengl, A. Bachofner, "Drastic Reduction of On-Resistance with COOLMOS™ ", pp. 250-258, PCIM Europe, 5 (1998).

[29] M. N. Darwish, “Study of the quasisaturation effect in VDMOS transistors,” IEEE Trans. Electron Devices, vol. ED-33, p. 1710, 1986.

[30] Chung-Min Liu and James B. Kuo, “Quasi-Saturation Capacitance Behavior of a DMOS Device,” IEEE TRANSACTIONS ON

ELECTRON DEVICES, VOL. 44, NO. 7, JULY 1997

[31]P. M. Shenoy, A. Bhalla, and G. M. Dolny, “Analysis of the effect of charge imbalance on the static and dynamic characteristics of the super junction MOSFET,” Power Semiconductor Devices and ICs, 1999. ISPSD '99. Proceedings.

[32]T. Fujihira and Y. Miyasaka, “Simulated superior performances of semiconductor super junction devices,” Proc. of the ISPSD, pp.

423-426, June, 1998.

[33] L. Lorem M. Man and G. Deboy, “COOLMOS - An important milestone towards a new power MOSFET generation”, Proc. of Power Conversion, pp. 151-160, May, 1998.

[34] G. Deboy, M. Marq J.P. Stengl, H. Strack, J. Thanyi and H. Weber,

“A new generation of high voltage MOSFETs breaks the limit line of silicon”, Proc. Of the IEDM, pp. 683-685, December, 1998.

(a) DMOS (b) UMOS Fig. 1.1 silicon power MOSFET structures

Fig. 1.2 Insulated gate bipolar transistor (IGBT) structure

Fig. 1.3 Cross section of the CoolMOS

Fig. 1.4 COOLMOS^TM on SOI wafer

Fig. 2.1 simulation of drift layer structures

Fig. 2.2 Electric field at conventional drift region

Fig. 2.3 Electric field for SJ structure

Fig. 2.4 Electric field profile along the right of the device, for SJ structures of heights 15 μm and 25μm

Fig. 2.5 The sketch map of the CoolMOS in the ON-state

Fig. 2.6 Output characteristics of the CoolMOS^TM transistor

Fig. 2.7 structure identical to the pillar region

Fig. 3.1 The manuals of ISE-TACD

x

Fig. 3.2 The simulated shape of the SJ structure

y

x

Fig. 3.3 The simulated shape of the CoolMOS structure

Fig. 4.1 Electric field distribution for SJ structure

Fig. 4.2 The electric field and electron density for N a = N d = 3 × 10¹⁵ at off-state (Vg = 0) in x=5

(V/cm)

(V/cm)

Fig. 4.3 The electric field and electron density for N a = N d = 6 × 10¹⁵ at off-state (Vg = 0) in x=5

Fig. 4.4 The electric field and electron density for N a = N d = 9 × 10¹⁵ at off-state (Vg = 0) in x=5

(V/cm)

(V/cm)

Fig. 4.5 The Id-Vg curve at Vd =100 V with different pillar concentrations

Fig. 4.6 Id-Vg curve at low Vd for Npillar=6×10¹⁵ cm^-3

Fig. 4.7 The Id-Vd curve for Npillar=3×10¹⁵ cm^-3

Fig. 4.8 The Id-Vd curve for Npillar=6×10¹⁵ cm^-3

Fig. 4.9 The Id-Vd curve for Npillar=9×10¹⁵ cm^-3

Fig. 4.10 The Id-Vd curves for multiple pillar concentrations

Fig. 4.11 The electric field distribution in off-state at Y=-9 for Npillar=6×10¹⁵ cm^-3

Fig. 4.12 The 2-D map of the electric field distribution in off-state at Vd=300V for Npillar=6×10¹⁵ cm^-3

Fig. 4.13 The 2-D map of the space charge distribution in on-state at 50V, 100V, 150V, 200V, and 300V for Npillar=6×10¹⁵ cm^-3

Fig. 4.14 The electric field and electron density for N a = N d = 9×10¹⁵ at on-state (Vg = 15) in x=5

Vd =10 V Vd = 20 V Vd = 30 V

Fig. 4.15 The Space charge (cm^-3) distribution for Vg = 5 V

Vd =10 V Vd = 20 V Vd = 30 V

Fig. 4.16 The Electric Field (V/cm) distribution for Vg = 5 V

Fig. 4.17 Electron density along x = 5 within saturation condition

Vd =20 V Vd = 40 V Vd = 60 V

Fig. 4.18 The Space charge (cm^-3) distribution for Vg = 10 V

Vd =20 V Vd = 40 V Vd = 60 V

Fig. 4.19 The Electric Field (V/cm) distribution for Vg = 10 V

Vg = 5 V Vg = 10 V

Fig. 4.20 The space charge, electron density and potential distribution at Vd = 30 V

Fig. 4.21 The Id-Vd curves at Vg = 15 V for pillar concentration imbalance

Fig. 4.22 The Id-Vd curves at Vg = 15 V for pillar concentration different

Fig. 4.23 The 2-D map of the space charge distribution at Vg = 15V for N a = 9×10¹⁵ cm^-3and N d = 6×10¹⁵ cm^-3

Fig. 4.24 The 2-D map of the space charge distribution at Vg = 15V for N a = 9×10¹⁵ cm^-3and N d = 9×10¹⁵ cm^-3

Fig. 4.25 Space charge distribution along y = -9 at Vd = 300 V N d = 9×10¹⁵ cm^-3 N d = 6×10¹⁵ cm^-3

簡歷

姓 名：李家明 性 別：男

出生日期：民國 70 年 4 月 3 日 出 生 地：台灣省台南市

住 址：台南市中華南路二段 258 號四樓

學 歷：國立台南一中 (民國 85 年 9 月~民國 88 年 6 月) 國立中山大學電機工程系 (民國 88 年 9 月~民國 93 年 6 月) 國立交通大學電子工程所 (民國 93 年 9 月~民國 95 年 9 月)

碩士論文：高功率元件-CoolMOS^TM的元件模擬與電性研究

A Study of Device Simulation and Electrical Properties for High Power Device-CoolMOS^TM