Critical Issu A

adopted in the areas of nanocrystalline dots memories. For example, the product of the gate voltage shift between two subsequent Coulomb Blockade events and the gate-to-dot coupling coefficient can be directly connected to the critical energy required to overcome the barrier due to the single electron storage energy and the quantum confinement induced energy separation. The single electron storage energy is defined the Coulomb energy ∆E ≈ q²/2Cdot where Cdot is the self capacitance of the dot.

Obviously, different situations encountered can lead to different definitions on the Coulomb energy.

2.5 Critical Issu

Due to the usage

Thomas-Fermi screening length instead as employed in the metal case. However, a

self-n Charge

he Coulomb energy also includes the contribution by the charge induced at the epletion region. The corresponding amount of energy is the p

consistent Schrödinger-Poisson solving over the range of gate voltage under study reveals a band bending across a poly depletion region near the oxide. The corresponding electron density at the interface is found to be about one order of magnitude less than the immobile positively charged impurity concentration. Hence, in the presence of the poly depletion in our work, the Debye-Hueckel screening length considerably applies, which should be much larger than the Thomas-Fermi screening length (of the order of 1 nm) in the metal gate case. To further support this argument, from the measured RTS relative amplitude at Vg = 0.2 V, we estimate the amount of the affected area to be at least 28 nm and 35 nm across the charged trap for zT = 0.7 nm and zT = 0 nm, respectively. Thus, the cited 70 nm for the Debye screening length remains reasonable. Even the replacement with a lower value of 28 nm or 35 nm causes little error.

B. Silicon Depletio T

edge of the semiconductor d

roduct of the induced charge at the edge of the semiconductor depletion region times the difference (∼ 0.07 eV) between Fermi level and valence band edge at the bulk part of the substrate. The depletion image charge at Vg = 0.2 V is found to be 0.1e and 0.07e, respectively, for zT = 0 and 0.7 nm, and each decreases with increasing gate voltage. As a result, the Coulomb energy due to the depletion image charge becomes of the order of a few meV and drops with increasing gate voltage.

Obviously, the role of the charge induced at the edge of the semiconductor depletion region is so insignificant that the depletion image charge can be neglected in the present work.

C. Electron Tunneling

First of all, a deeper oxide trap may not always dictate a longer time. According ordinate diagrams that describe the electron-lattice coupling, our

Fig.

to the configuration co

data point to the opposite case: a deeper oxide trap produces a smaller time constant. This is reasonable since all the extracted parameters can find their physical origins as detailed above. If the electron tunneling were involved only, then the capture time would be the sum of the tunneling time from the channel conduction band edge to certain oxide depth zT plus the subsequent multiphonon emission time such as to lower the energy of the tunneling electrons to the same level as the trap.

One can estimate the tunneling time of around 10^-9 sec across zT of 0.7 nm [16] and can reasonably hypothesize that the multiphonon emission time is a spontaneous event (as can be easily understood from the configuration coordinate diagrams in Fig.

2.6; the hypothesis also works well for the areas of the trap assisted tunneling), leading to a capture time of the order of 10^-9 sec. Obviously, the possibility of the electron tunneling must in principle be removed since the measured capture times fall within 0.5 to 6 sec. On the other hand, once trapped the electrons may instantly tunnel to the gate electrode, contributing to the gate current. In other words, under such situations, no RTS in drain or gate current can be detected due to the extremely slow detection process in measurement setup. Moreover, in our work the gate current was found to be several orders of magnitude less than the drain current, indicating the absence of the electron tunneling in determining the experimental RTS drain current.

Note that the high and low levels of RTS current represent the different stable states as denoted the free and bound state in the configuration coordinate diagrams in

2.6. The detailed balance essentially applies only to such two states, rather than the abrupt transitions between the two. The capture and emission time constants represent the critical times required to overcome the barrier height and reach the

crossing point, then instantly entering into the other stable state.

Eventually, the measured discrete switching RTS drain current indicates that the transit time between the high and low level is substantially less than the integration time

2.6 Conclusion

gy OS system with a nanometer-scale oxide trap. Other corroborating in measurement setup [10]. In other words, the abrupt transition between two stable states represents a spontaneous event with respect to the measurement setup.

Hence, the corresponding transient displacement current through the gate electrode may escape detection. This explains why we saw only a flat gate current level (with typical thermal or shot fluctuations around it) over the whole observation time.

We have presented experimental evidence concerning the Coulomb ener enhancement in a M

evidence based on a multiphonon theory has elucidated the measured capture and emission kinetics. The corresponding configuration coordinate diagrams have been established. We have further elaborated on the clarification of the Coulomb energy and have differentiated it from that in memories containing nanocrystals as a floating gate.

Some critical issues encountered in the work have been addressed as well.

References

[1] M. Schulz, “Coulomb energy of traps in semiconductor space-charge regions,” J.

lz, “Evaluation of the Coulomb energy for

be, and K. Chan, “A silicon

ansistor

ition

da, “Electron trapping, storing, and

. A. Fetter, R. W. Epworth

. A. Buhrman, “Localized-State Interactions in

. J. Kirton and M. J. Uren, “Noise in solid-state microstructures: a new Appl. Phys., vol. 74, pp. 2649-2657, 1993.

[2] H. H. Mueller, D. Wörle, and M. Schu

single-electron interface trapping in sub-µm metal-oxide-semiconductor field-effect transistors,” J. Appl. Phys., vol. 75, pp. 2970-2979, 1994.

[3] S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. F. Crab

nanocrystals based memory,” Appl. Phys. Lett., vol. 68, pp. 1377-1379, 1996.

[4] L. Guo, E. Leobandung, and S. Y. Chou, “A Silicon Single-Electron Tr Memory Operating at Room Temperature,” Science, vol. 275, pp. 649-651, 1997.

[5] M. Saitoh, N. Takahashi, H. Ishikuro, and T. Hiramoto, “Large Electron Add Energy above 250 meV in a Silicon Quantum Dot in a Single-Electron Transistor,”

Jpn. J. Appl. Phys., vol. 40, pp. 2010-2012, 2001.

[6] S. Huang, S. Banerjee, R. T. Tung, and S. O

emission in nanocrystalline Si dots by capacitance–voltage and conductance–voltage measurements,” J. Appl. Phys., vol. 93, pp. 576-581, 2003.

[7] K. S. Ralls, W. J. Skocpol, L. D. Jackel, R. E. Howard, L

and D. M. Tennant, “Discrete Resistance Switching in Submicrometer Silicon Inversion Layers: Individual Interface Traps and Low-Frequency (1/f?) Noise,” Phys.

Rev. Lett., vol. 52, pp. 228-231, 1984.

[8] K. R. Farmer, C. T. Rogers, and R

Metal-Oxide-Semiconductor Tunnel Diodes,” Phys. Rev. Lett., vol. 58, pp. 2255-2258, 1987.

[9] M

perspective on individual defects, interface states and low-frequency (1/f) noise,” Adv.

Phys., vol. 38, pp. 367-468, 1989.

[10] M. J. Chen and M. P. Lu, “On–off switching of edge direct tunneling currents in

. Krautschneider, and S. Schwantes, “Observation and modeling of

eep Centers in Semiconductors, edited by S. T. Pantelides (Gordon

rocesses in Semiconductors, 3rd ed.(Clarendon, Oxford,

. Palma, A. Godoy, J. A. Jiménez-Tejada, J. E. Carceller and J. A.

. Rudra, M. E. Zvanut and F. J. Feigl, “Hysteresis and

C. Svensson, “Tunneling to traps in insulators,” J. Appl. Phys., metal-oxide-semiconductor field-effect transistors,” Appl. Phys. Lett., vol. 81, pp.

3488-3490, 2002.

[11] A. Avellan, W

random telegraph signals in the gate and drain currents of tunneling metal–oxide–semiconductor field-effect transistors,” Appl. Phys. Lett., vol. 78, pp.

2790-1792, 2001.

[12] D. V. Lang, D

and Breach, Yverdon, 1992).

[13] B. K. Ridley, Quantum P 1993).

[14] A

López-Villanueva, “Quantum two-dimensional calculation of time constants of random telegraph signals in metal-oxide–semiconductor structures,” Phys. Rev. B, vol.

56, pp. 9565-9574, 1997.

[15] W. B. Fowler, J. K

Franck-Condon relaxation in insulator-semiconductor tunneling,” Phys. Rev. B, vol. 41, pp. 8313-8317, 1990.

[16] I. Lundström and

vol. 43, pp. 5045-5047, 1972.

0.15 0.20 0.25 0.30 0.35 0.40 0.45

0.15 0.20 0.25 0.30 0.35 0.40 0.45

10

Fig. 2.1 Measured mean capture time to mean emission time ratio versus gate voltage for two devices labeled Trap A and Trap B. The inset shows the time records of RTS drain current at a fixed gate voltage of 0.3 V. The fitting lines from (2) are also shown.

Q dep