DC BIAS EFFECT

Fig. 4-1 shows the cross-section of the conventional top-contact pentacene-based OTFTs used in this study Firstly, 100-nm-thick thermal oxide was grown on heavily doped Si wafers to serve as the gate dielectric. Then, pentacene obtained from Aldrich without any purification was evaporated through shadow mask onto the thermal oxide to form the active layer. The deposition rate was controlled at 0.5Å/s while the substrate temperature was kept as 70°C. After the formation of 100-nm-thick pentacene, 100-nm-thick

gold was deposited through the shadow mask to form the source/drain contacts. The device channel width and length were defined as 1000 μm and 600 μm, respectively. Two series of bias-stress measurements were performed: one with zero drain bias and various gate biases and the other with a fixed gate bias and different drain biases.

4-1. Only VG bias, no VD bias

Firstly, we analyze the Bias stress effect with zero drain bias. The linear-region transfer characteristics of the devices before stress and after 2000-sec stress are depicted in Fig. 4-2. With source and drain connected to ground, negative gate biase were used as the stress conditions (VDS = 0 V, VG – Vthini = -15V), where Vthini is the initial threshold voltage). The negative gate-bias stress causes a shift of the transfer characteristics while the subthreshold swing stays almost unchanged. The threshold voltage Vth , subthreshold swing and the field-effect mobility μFE as a function of stress time are shown in Fig. 4-3 and Fig. 4-4, respectively. Apparently μFE is not affected by the stress, while Vth is drastically changed[27] [28]. Such a phenomenon is often believed to be caused by the generation of deep states with long discharge time that degrade Vth. The shallow traps that would affect μFE may not be changed by the gate bias stress . The power-law dependence between the threshold voltage shift and the stress time is also found in Fig. 4-5. This can be explained by the approximation of the OTFT BSE model, in which the stretched exponential function reduces to the simple power-law function when the stress time is much less than the effective trapping time τ. when the stretched exponential function is used, the dispersion parameter β can be

obtained by plotting ^log

{

}

shown in Fig. 4-6. After extracting β = 0.283 and defining the attempt to escape

frequency ν = 10⁵ Hz, the effective trapping time τ and the mean activation energy for the defect generation EA can be determined by fitting with the stretched exponential function shown in Fig. 4-7 . The resulting E

VT

Δ

A is 0.57 eV and τ is 36127 sec at room temperature.

4-1-2. Recovery

Devices subjected to bias stress recover to their original state within a few hours when left in the dark shown in Fig. 4-8 and at the end of the recovery process, the transfer characteristic is essentially identical to that of the unstressed state. The cycle of stress and recovery was repeated with no any change in behavior. Even though the recovery mechanism is still not clearly understood, recombination of the trapped holes with free electrons is proposed to be a plausible reason[29].

4-1-3. Influence of positive VG bias on stress and recovery

Under the same condition as negative gate stress, The stress gate voltage changes to +6V. Because of the presence of pentacene layer at the

source/drain contacts, only the hole conduction characteristics are observed.

The characteristics have positive shifts under +6V Bias stress. The evolution of the threshold voltage shift extracted from the curve is shown in Fig. 4-9.As shown in Fig. 4-10, the recovery curves of two identical OTFTs after stress are compared. When the positive gate bias (VGS = +4V) is added to induce electrons, the recovery of the device is faster than that of the device without positive gate bias. At the 1000s, the threshold voltage shift over the original value become positive under the +4V gate bias and with the discussion in the early part of this section, these results lead us to the conclusion that the positive gate bias not just increase the recovery also include the positive bias effect. This means that electrons can be used to remove defect states or more negative defect states are generated to compensate the threshold voltage shift[29].

4-2. Fix VG bias stress, various VD bias stress

Then, different drain biases (VDS = 0 V, -5 V, -10 V, and -15 V) were added to the bias-stress measurement while the gate bias was fixed as VG – Vthini = -15 V. The μFE and the subthreshold swing extracted from devices with different stress conditions are plotted as a function of stress time in Fig. 4-11.

T

Unchanged μFE and subthreshold are observed, and consequently the influence of drain-bias stress on the shallow traps can be excluded. The influence of drain-bias stress on the Vth, however, is significant. As shown in Fig. 4-12, the threshold voltage shift ΔVth is suppressed when the drain bias becomes more negative. All the relationships depicted in Fig. 4-13 follow the power-law dependence with identical slope. According to the BSE model, the slope represents the dispersion parameter β that influences the relaxation and the dispersive transport of disorder system. Identical β value implies that the microscopic processes of the state creation such as the impurity diffusion or the defect creation kinetics should be independent of the drain bias. The influence of drain bias on the carrier concentration is believed, as in a-Si TFTs, to be the dominant reason that causes the ΔVth to be dependent on VDS.

To quantitatively discuss this relationship, for a given VGS, we define the relative threshold voltage shift ΔV^rel as the ratio between the ΔVth with various VDS stress and the ΔVth with zero drain-bias stress. Since the defect generation rate is proportional to the carrier density, the influence of drain bias on the carrier density in the accumulation channel should be considered. For simplicity, the channel charge normalization factor (QG0/QG) proposed is used[16]. As a result, Stretched-exponential equation is modified as:

⎪⎭ The calculated normalized channel charge is defined QG /QG0 , where QG

is the channel charge when VD is varied and QG0 is the channel charge when VDS = 0V. Good agreement can be observed between and the calculated Q

rel

VT

Δ

G /QG0 curve. The result verifies the proportionate relationship between the defect creation rate and the carrier concentration. Also, the result suggests that convergent data can be obtained by plotting the restored threshold voltage shift ΔV_T^res= (QG0 / QG)ΔVth as a function of stress time as shown in Fig. 4-14. The restored threshold voltage shift excludes the drain bias effect and can be used to extract the parameters associated with the defect creation kinetics. For example, when the stretched exponential function is used, the dispersion parameter β can be obtained by plotting

res

After extracting β = 0.283 and defining the attempt to escape frequency ν = 10⁵ Hz, the effective trapping time τ and the mean activation energy for the defect generation EA can be determined by fitting ΔV_T^res with the stretched

exponential function. The resulting EA is 0.57 eV and τ is 36127 sec at room temperature.

4-2-2. Recovery with VD

Finally, the drain bias effect on the threshold voltage recovery is addressed. It is expected that the positive drain bias reduces the electron amount and suppresses the recovery rate. As shown in Fig. 4-15, the recovery curves of two identical OTFTs after stress are compared. When the same positive gate bias (VGS = 4V) is added to induce electrons, the recovery of the device without the drain bias is faster than that of the device with a positive drain bias (VDS = 4V). This result gives an insight of the recovery mechanism;

though a comprehensive understanding should be carefully studied in future work.

Chapter 5