DDR SDRAM C ONCEPT

Before introducing SSTL_2 and DLL, simply understanding DDR SDRAM architecture is necessary. The DDR SDRAM transfers data at the rate of 200, 266, 333,

and 400 Mbps. Its clock speed is 100, 133, 166, 200 MHz. DDR SDRAM transfer data at both rising and falling edge of clock. The conventional SDR SDRAM only fetches data at rising edge of clock. But DDR SDRAM spends one cycle in employing 2-bit prefetch architecture. DDR SDRAM transfers data twice in a period of clock cycle, and SDR SDRAM only transfers one time in a period of clock cycle. DDR SDRAM transfers data twice than SDR SDRAM when they are operated in the same frequency so that DDR SDRAM can have higher data rate without increasing clock frequency. But it is difficult to accurately control the data input/output timing based on the conventional single clock. Therefore, DDR SDRAM adopts a differential clock scheme that enables accurate memory control. The duty cycle of clock has to keep about 50% to prevent timing error. This is not the same as SDR SDRAM. Because SDR SDRAM can make the high state a little less than the low state. This can prevent next data transferred earlier than expected. But DDR SDRAM should keep the duty cycle about 50% as accurately as possible. The internal clock is generated by the external clock across long wire line or clock tree. This may influence the accuracy of timing. So DLL is used here to lock the internal clock referred to the external clock.

DLL would generate the internal clock that has duty cycle about 50%. The detail about DLL will be discussed in chapter 4. DDR SDRAM employs SSTL_2 interface to eliminate the signal degradation caused by noise and reflection produced as a result of a high operating frequency. SSTL_2 is a low-voltage (2.5 V), amplitude and high-speed interface that reduce the effect of reflection by connecting series resistance between the signal branch point from the bus and the memory. There are another technologies used in DDR SDRAM architecture in [1] - [3]. The comparisons of DDR and SDR SDRAM are listed in Table 1.1.

1.3 SSLT_2I/OCIRCUIT ARCHITECTURE

Fig. 1.1 shows the concept of SSTL_2 architecture. The output of SSTL_2 transmitter is CMOS buffer. The CMOS buffer should provide 8.1mA output current for Class_I, and 16.2 mA output current for Class_II. The receiver of SSTL_2 is a differential pair. One input of this differential pair is connected to reference voltage which value is 0.5xV_DDQ. Another is connected to the input pin of the receiver. When receiver receives data, the input pin of the receiver compares with reference voltage.

The data is judged to be ‘1’ when the voltage of input pin is larger than reference voltage, and to be ‘0’ when the voltage of input pin is smaller than reference voltage.

RS is called stub resistance. It is connected in series to the output pin (Vout) that provides impedance matching between the transmission line and device output. The termination voltage (V_TT) is terminated with RT. The value of termination voltage is the same as reference voltage. The value of RT in Class_I is different to in Class_II. It will be explained in following chapter. And SSTL_2 uses terminal resistance (RT) connected to termination voltage to reduce the swing range to increase the speed.

Otherwise, this termination suppresses signal reflection in the transmission line and also reduces voltage spikes, enabling high-speed data transmission.

1.4 DLLARCHITECTURE

DLL applied in DDR SDRAM is designed to realize a fast access time and high operation frequencies by controlling and adjusting the time lag between the external clock and internal clock. The block diagram of conventional DLL architecture is shown in Fig. 1.2. The comparator compares the external clock and feedback of internal clock. Then the arbiter and finite state machine (FSM) receive the result of

comparator and sends up or down signal to up/down counter. And decoder will decode the signal of up/down counter to control the delay line to lock the internal clock referring to external clock. There are many methods to realize DLL architecture such as digital DLL, analog DLL, and mixed-mode DLL. These different types of DLL architecture have their individual advantages and disadvantage. Judging whether they are significant or not is important in designing DLL architecture applied in DDR SDRAM.

1.5 THESIS ORGANIZATION

Chapter 2 of this thesis discusses the SSTL_2 standard. The detail DC and AC specifications and some features of DLL will be presented in this chapter. Chapter 3, two version design of SSTL_2 I/O circuit are presented and the measurement results are shown in the last section of this chapter. Chapter 4 discusses DLL architecture design more detail. We will discuss all blocks of this DLL architecture design, and explain how these blocks operate. Summarizing this thesis and making some conclusions are described in the last chapter.

Table 1.1

Difference in functions and specifications between DDR and SDR SDRAM.

Item DDR SDRAM SDR SDRAM Data Transfer Frequency Twice the Operation

Frequency

Same as the Operation Frequency

Data Rate 2/tclock 1/tclock

Clock Input Differential Clock Single Clock

Data Strobe Signal(DQS) Essential Not Support

Interface SSTL_2 LVTTL

Supply Voltage 2.5 V 3.3 V

CAS Read Latency 2, 2.5 2, 3

CAS Write Latency 1 0

Burst Length 2, 4, 8 1, 2, 4, 8 Full-Page(256)*

Burst Sequence Sequential/Interleave Sequential/Interleave

Use of DLL Essential Optional

Data Mask Write Mask Only Write Mask/Read Mask

* Full-Page(256) burst of SDR SDRAM is an option.

Fig. 1.1 Concept of SSTL_2 Architecture

Fig. 1.2 Block Diagram of DLL Architecture

Chapter 2

Specifications of Stub Series Terminated Logic for 2.5 V (SSTL_2) Standard and Delay-Locked Loop (DLL) Standard

2.1 BACKGROUND

For high frequency memory application, the data transfer must resist the noise or signal reflection through the transmission line. Although internal circuits may achieve hundreds megabits-per-second even gigabits-per-second range, the I/O circuits may not support such high frequency. So even the memory uses the newest process, algorithm, and architecture to satisfy the speed what we want to achieve, it can still not output the signal at this operational frequency. In SDR SDRAM, LVTTL is applied as the I/O interface. But in DDR SDRAM, the data rate would reach to 400 Mbps. The LVTTL may not be suitable for DDR SDRAM interface at this frequency because LVTTL didn’t have enough noise margins and operation frequency. In such high speed, to enable data transmission and to suppress noise influences are the main factors in interface determinant. SSTL_2 uses termination resistance connected to termination voltage to suppress signal reflection in the transmission line, to reduce voltage spikes, and to enable high-speed data transmission. So SSTL_2 is suitable to the DDR SDRAM interface. Otherwise, high-speed data transmission should emphasis the subject of timing. Providing accurate clock is significant to data transmission. DLL can realize a fast access time and high operation frequencies so that it is often applied in the DDR SDRAM architecture. DLL provide a differential

pair of clock locked as the external clock to be sure that the data transmission can meet the accurate timing.

2.2 STANDARD OF SSTL_2

The interface applied in DDR SDRAM is defined by the document, Stub Series Terminated Logic for 2.5 V (SSTL_2) JESD8-9B [4]. This JEDEC standard document defines the AC voltage level, DC voltage level, minimum output current, and all voltage sources needed in the SSTL_2 circuit. Also it shows the concept of two types SSTL_2 I/O circuits, Class_I I/O circuit and Class_II I/O circuit, and roughly compares the differences between Class_I and Class_II I/O circuit.

2.2.1 Concepts of Two Types SSTL_2 I/O Circuits

SSTL_2 output buffer is mainly compartmentalized Class_I and Class_II I/O circuit. Fig. 2.1 shows the SSTL_2 architecture. RS is the stub resistance, whose value is 25 Ω, connected in series to output pin. The stub resistance provides impedance matching between the device output and transmission line. RT has different value in Class_I and Class_II application. In Class_I architecture RT is 50 Ω, and RT is 25 Ω in Class_II architecture. In actual application, there is transmission line connecting RS and RT. So RT is a concept of equivalent impedance looking from the end of RS. The detail description of SSTL_2 output connection will be discussed in the next chapter.

Otherwise, Class_I and Class_II are also different in the aspect of electric characteristics. It will be shown in section 2.2.4, output buffer electric characteristic.

Otherwise, the receiver of SSTL_2 has two ways to receive data. This thesis emphasizes discussing single-ended signal. The single-ended signal receiver has input

pin of reference voltage, Vref. At the mention of receiver before, the receiver has a differential pair to receive data. One input pin of this differential pair has the function of the receiver input pin. Another is connected to the reference voltage, Vref. In the later chapter, the single-ended signal receiver will be emphasis. The different part between single-ended and differential signals receiver is that the pin which is connected to reference voltage is changed to be connected to the inverse phase of the output data. Tables 2.1 and 2.2 list the DC and AC logic levels and AC test conditions about differential input, and Fig. 2.2 shows the waveform of SSTL_2 differential input levels simply. In Fig. 2.2, V_TR means the “true” input level, and V_CP means the

“complementary” input level. VIN(DC) is defined the allowable DC excursion of each differential input. V_Swing(DC) / V_Swing(AC)is the absolute value of the DC/AC value difference between the “true” input level and the “complementary” input level. VX(AC)

is the crossing point of V_TR and V_CP. The typical value of V_X(AC) is expected to be about 0.5x VDDQ of the transmission device and VX(AC) is expected to track variations in V_DDQ. V_X(AC) indicates the voltage at which differential input signals must be crossing. Table 2.2 lists the differential input AC test conditions. Fig. 2.3 and Fig. 2.4 are two examples of SSTL_2 Class_I differential signals AC test conditions. Those figures can simply explain the different part between single-ended and differential signals I/O circuits. In later chapter, the single-ended signal I/O circuit will be discussed mainly.

2.2.2 Supply Voltage Levels

All circuits have to need power to make them work normally. First, supply voltage levels must be defined. Table 2.3 lists the supply voltage levels. For explaining SSTL_2 circuits more clearly, Fig. 1.1 is repeated here again as Fig 2.5.

V_DDQ is the output supply voltage. It provide the output buffer a pair of separate power lines, because the output buffer must source and sink large amount of current.

It would make the control circuits influenced by the ground bounce and power bounce which is induced by the large amount of output current. So the control circuit power line can be separated from the output buffer power line. Table 2.3 defines the relationship between VDD and VDDQ. There is no specific device VDD supply voltage requirement for SSTL_2 compliance. However, under all conditions V_DDQ must be less than or equal to VDD. Otherwise, the input reference voltage, Vref, may be selected by the user to provide optimum noise margin in the system. Typically the value of Vref is expected to be (0.49~0.51)xVDDQ of the transmitting device and Vref is expected to track variations in V_DDQ. And peak to peak AC noise on Vref may not exceed +/-2% of Vref(DC). The terminated voltage also has relationship to Vref. VTT of transmitting device must track Vref of receiving device. Because the SSTL_2 I/O circuits receive data from internal circuits and transmit data to internal circuits, they need a pair of low voltage, 1.2 V, to supply the circuits be able to transfer data with internal circuits correctly. In the aspect of low voltage power line is not defined accurately.

2.2.3 Input Logic Electric Characteristics

Input logic levels are shown in Table 2.4. We can reference Fig. 2.6 to understand the relationship of the input logic levels more clearly. Within this standard, it is the relationship of the VDDQ of the driving and the Vref of the receiving device that determines noise margins. However, in the case if V_IH(MAX) (i.e. input overdrive) it is the VDD of the receiving device that is referenced. In the case where a device is implemented that supports SSTL_2 inputs but has no SSTL_2 outputs, and therefore

no V_DDQ supply voltage connection, inputs must tolerate input overdrive to 3.0 V (High corner VDDQ+300mV). Otherwise, VIH and VIL both have AC and DC value definition. The DC value is defined smaller than AC value. It means that the hysteresis zone of the AC value is larger than the DC value’s. Since the AC value is less stable than DC value, AC value must need larger noise margins than DC value.

When receiver receives continual low or high signals, the signals can be treated as the DC values. The AC value of V_IH and V_IL must have larger noise margins than DC value of VIH and VIL to defend the noise affecting. Then, Table 2.5 shows the AC input test conditions. The AC input test conditions are specified to be able to obtain reliable, reproducible test results in an automated test environment, where a relatively high noise environment makes it difficult to create clean signals with limited swing.

The AC test conditions may be measured under nominal voltage conditions as long as the supplier can demonstrate by analysis that the device will meet its timing specifications under all supported voltage conditions. For VSwingmax, the input signal maximum peak to peak swing, compliant devices must still meet the V_IH(AC) and VIL(AC) specifications under actual use conditions. The 1 V/ns input signal minimum slew rate is to be maintained in the V_ILmax(AC) to V_IHmin(AC) rage of the input signal swing. Fig 2.7 shows the AC input signal wave form of Table 2.5.

2.2.4 Output Buffer Electric Characteristics

The output part of SSTL_2 is composed of CMOS buffer. The specifications of output buffer electric characteristics sets minimum requirements for output buffers in such a way that when they are applied within the range of power supply voltage specified in SSTL_2 and are used in conjunction with SSTL_2 input receivers then the input receiver specifications can be met or exceeded. The specifications are quite

different from traditional specifications, where minimum values for V_OH and maximum values for VOL are set that apply to the entire supply range. In SSTL_2, the input voltage provided to the receiver depends on the driver as well as on the termination voltage and termination resistors. Of particular interest here are the values V_OUT and V_IN. These values depend not only on the current drive capabilities of the buffer, but also on the values of VDDQ and VTT (Vref is equal to VTT). The important condition is that V_IN be at least 405 mV above or below V_TT as a result of V_OUT attaining its maximum low or its minimum high value. As will be seen later, the two cases of interest for SSTL_2 are where the series resistor RS equals 25 Ω and the termination resistor RT equals 50 Ω (for Class_I) or 25 Ω (for Class_II). VTT is specified as being equal to 0.5x V_DDQ.

In order to meet the 405 mV minimum requirement for VIN, a minimum of 8.1 mA must be developed across RT if RT equals 50 Ω (Class_I) or 16.2 mA in case RT equals 25 Ω (Class_II). The driver specification now must guarantee that these values of V_IN are obtained in the worst case conditions specified by this standard. Table 2.6 and Table 2.7 codify Class_I output buffer DC current drives and AC test conditions.

Table 2.8 and Table 2.9 codify Class_II output buffer DC current drives and AC Test conditions. Table 2.10 is the spread sheet showing how the limits of SSTL_2 circuit voltage depend on V_DDQ. It shows some cases about the influence of the variation of Vref and VTT. In Table 2.10 the “on resistance” equals VTT/I - (RS+RT). The worst case assumption for V_TT results from the fact that for V_TT=V_TT(MIN) the input at the receiver is already biased towards the low state and less current will be required to develop 345 mV ΔVIN. If the driver maintains a resistance lower than the “Maximum On Resistance”, more than the 345 mV will be presented to the receiver.

These specifications are defined in the above sections. The SSTL_2 I/O circuits should obey these specifications to be designed to transfer data correctly. The more

detail aspect about the SSTL_2 I/O circuits will be discussed in next chapter.

2.3 STANDARD OF DLL

In DDR SDRAM, the DLL circuit, shown in Fig. 2.8, is designed to realize a fast access time and high operation frequency by controlling and adjusting the time lag between the external clock and internal clock. There are many ways to realize the DLL circuits, such as digital DLL architectures [5] - [8], analog DLL architectures [9], and mixed-mode DLL architectures [10]. The digital DLL architectures have the advantage of low power consumption and high operation frequency, and they have the disadvantage of more complex control circuits. The analog DLL architectures have the advantage of locking more precisely, and they have the disadvantage of high power consumption. The mixed-mode DLL architectures have the advantage of both digital and analog DLL architectures, and they have the disadvantage of large chip area and complex timing control. These types of DLL architectures have different advantages and disadvantages. Determining whether they are significant or not helps designer to decide which DLL architecture can be applied in the DDR SDRAM.

DLLs are now often used in the DDR SDRAM architecture in order to hide clock distribution delays and to improve overall system timing. In these applications, DLLs must closely track the input clock. However, the rising demand for the DDR SDRAM I/O interfaces has created an increasingly noisy environment in which DLLs must function. This noise, typically in the form of supply and substrate noise, tends to cause the output clock of DLLs to jitter from their ideal timing. Otherwise, for the demand of the duty cycle, the DLLs must output the internal clock with 50% duty cycle. So, with a shrinking tolerance for jitter in the decreasing period of the output clock, the design of low jitter DLLs has become very challenging. Here the

specification of the DLL which operation range is 66 MHz to 250 MHz reference clock frequency in DDR SDRAM application is defined. The delay adjustment range is 0% to 100% of input clock cycle in the range of operation frequency. The locking time is 150 input clock cycles. It means that no matter the reference input clock frequency is the output clock must be locked within 150 input clock cycles, and the range of the output clock duty cycle is 45% to 55%. The DLL current consumption is 10 mA. Table 2.11 codifies these specifications of the DLL architecture.

Table 2.1

Differential Input Logic Levels.

Symbol Parameter Minimum Maximum

VIN(DC) DC Input Signal Voltage -0.3 V VDDQ+0.3 V

VSwing(DC) DC Differential Input Voltage 0.3 V VDDQ+0.6 V VSwing(AC) AC Differential Input Voltage 0.62 V VDDQ+0.6 V V_X(AC) AC Differential Cross Point Voltage 0.5xV_DDQ-0.2 V 0.5xV_DDQ+0.2 V

Table 2.2 V_Swing Input Signal Peak To Peak Swing

Table 2.2 V_Swing Input Signal Peak To Peak Swing