C ONCLUSION

For these measurement results, the SSTL_2 I/O circuit with slew rate control circuit equips better performance than the first version SSTL_2 I/O circuit. It can be operated at the speed of 600 Mbps for eight bits SSTL_2 I/O circuit with slew rate control circuits operated at the same time without transferring wrong data. But at this operation frequency for two bits or three bits of the first version SSTL_2 I/O circuits, the duty cycle of this I/O circuit does no longer maintain at 50%. The SSTL_2 I/O circuit with slew rate control circuit may be able to be operated higher frequency, but the output signals are transferred by tapper buffers which limit the maximum operation frequency. Otherwise, for the DDR SDRAM application these two versions SSTL_2 I/O circuit can be operated normally (operating at the speed of 400Mbps).

Table 3.1 shows the electrical characteristics of these kinds of SSTL_2 I/O circuits.

The output enable time is defined the reaction time of the output node, Vout, after

“oen” is high. The current consumption of 2nd version Class_II type SSTL_2 I/O circuit is larger than the reference. This is because the size of output buffer may be larger than the reference due to the most current consumption produced by the output buffer of Class_II type SSTL_2 I/O circuit. Table 3.2 shows the HBM ESD testing of the I/O circuit. The ESD level of the I/O circuit is more than 5 kV. The HBM ESD testing for VDD-to-VSS Stress Positive-mode is 6kV.

Table 3.1

Fig. 3.1 Class_I type of SSTL_2 Architecture

Fig. 3.2 Class_II type of SSTL_2 Architecture (double-terminated output)

Fig. 3.3 Class_II type of SSTL_2 Architecture (single-terminated output)

Fig. 3.4 Concept of SSTL_2 Architecture

Fig. 3.5 SSTL_2 Applied in DIMM Architecture

Fig. 3.6 SSTL_2 Unterminated Output Load

Fig. 3.7 Block Diagram of SSTL_2 Transmitter

Fig. 3.8 Schematic of State Logic

Fig. 3.9 Schematic of Level Converter

Fig. 3.10 Schematic of SSTL_2 Receiver

Fig. 3.11 Control Circuit of SSTL_2 Class_I type

Fig. 3.12 SSTL_2 Class_I type I/O Circuit

Fig. 3.13 Control Circuit of SSTL_2 Class_II type

Fig. 3.14 SSTL_2 Class_II type I/O Circuit

Fig. 3.15 2.5V ESD Protection Circuit

Fig. 3.16 1.2V ESD Protection Circuit

Fig. 3.17 Block Diagram of SSTL_2 with Slew Rate Control

Fig. 3.18 Modified Level Converter

Fig. 3.19 Comparison of the Level Converter Simulation Result

Fig. 3.20 Modified Receiver

Fig. 3.21 Conventional Slew Rate Control Circuit of Output Buffer

Fig. 3.22 Modified Slew Rate Control Circuit of Output Buffer

Fig. 3.23 Measurement Environment Setup

Fig. 3.24 Class_I Test Circuit

Fig. 3.25 Class_II Test Circuit

Fig. 3.26 The Die Photo and Layout of 1st tap-out

Fig. 3.27 PCB Board of 1st tap-out Class_I Test Circuit

Fig. 3.28 Class_I Test Circuit Operated at 400 Mbps (200MHz)

Fig. 3.29 Class_I Test Circuit Operated at 500 Mbps (250MHz)

Fig. 3.30 PCB Board of 1st tap-out Class_II Test Circuit

Fig. 3.31 Class_II Test Circuit Operated at 400 Mbps (200MHz)

Fig. 3.32 Class_II Test Circuit Operated at 500 Mbps (250MHz)

Fig. 3.33 The Die Photo and Layout of 2nd tap-out

Fig. 3.34 PCB Board of 2nd tap-out Internal Circuit

Fig. 3.35 Class_I Test Circuit Operated at 400 Mbps (200MHz)

Fig. 3.36 Class_I Test Circuit Operated at 500 Mbps (250MHz)

Fig. 3.37 Class_I Test Circuit Operated at 600 Mbps (300MHz)

Fig. 3.38 Class_II Test Circuit Operated at 400 Mbps (200MHz)

Fig. 3.39 Class_II Test Circuit Operated at 500 Mbps (250MHz)

Fig. 3.40 Class_II Test Circuit Operated at 600 Mbps (300MHz)

Fig. 3.41 PCB Board of 2nd tap-out Internal Circuit

Fig. 3.42 1 bit Class_I Test Circuit Operated at 400 Mbps (200MHz)

Fig. 3.43 1 bit Class_I Test Circuit Operated at 500 Mbps (250MHz)

Fig. 3.44 1 bit Class_I Test Circuit Operated at 600 Mbps (300MHz)

Fig. 3.45 1 bit Class_II Test Circuit Operated at 400 Mbps (200MHz)

Fig. 3.46 1 bit Class_II Test Circuit Operated at 500 Mbps (250MHz)

Fig. 3.47 1 bit Class_II Test Circuit Operated at 600 Mbps (300MHz)

Fig. 3.48 8 bits Class_I Test Circuit Operated at 400 Mbps (200MHz)

Fig. 3.49 8 bits Class_I Test Circuit Operated at 500 Mbps (250MHz)

Fig. 3.50 8 bits Class_I Test Circuit Operated at 600 Mbps (300MHz)

Fig. 3.51 8 bits Class_II Test Circuit Operated at 400 Mbps (200MHz)

Fig. 3.52 8 bits Class_II Test Circuit Operated at 500 Mbps (250MHz)

Fig. 3.53 8 bits Class_II Test Circuit Operated at 600 Mbps (300MHz)

Fig. 3.54 8 bits Class_II Test Circuit Operated at 666 Mbps (333MHz)

Chapter 4

Delay-Locked Loop

4.1 INTRODUCTION

DDR SDRAM is required a DLL (Delay-Locked Loop) circuits. The DLL circuit is designed to realize a fast access time and high operation frequencies by controlling and adjusting the time lag between the external clock and internal clock. As mentioned in previous chapter, the DLL is divided in three types architecture, digital, analog, and mixed-mode DLL architectures. The digital DLL architectures have the advantage of low power consumption and high operation frequency, and they have the disadvantage of more complex control circuits. The analog DLL architectures have the advantage of locking more precisely, and they have the disadvantage of high power consumption. The mixed-mode DLL architectures have the advantage of both digital and analog DLL architectures, and they have the disadvantage of large chip area and complex timing control. These types of DLL architectures have different advantages and disadvantages. Determining whether they are significant or not helps designer to decide which DLL architecture can be applied in the DDR SDRAM. Here, the digital DLL architectures applied in DDR SDRAM will be designed in this chapter.

4.2 BASIC DLLARCHITECTURE

The conventional DLL architectures include delay line, decoder, up/down counter, arbiter, finite state machine (FSM), and comparator. The block diagram of

conventional DLL architecture is shown in Fig. 4.1. DLL applies the comparator to compare the feedback clock. There are many methods to fetch the feedback clock for comparison so that there are different ways to realize the comparator. Then, the arbiter will judge and send the command to the FSM. The FSM will decide whether the up/down counter should be increased or decreased. The decoder decodes the up/down counter data to control the delay line to adjust the internal clock to deduce the difference between external clock and internal clock. In next section the modified DLL architecture.

4.3 DLLCIRCUIT IMPLEMENTATION

This section discusses the modified DLL architecture, shown in Fig. 4.2. This DLL architecture compares the external clock and the internal clock every two clock cycles by applying the divider. The divider, shown in Fig. 4.3, is composed of a D Flip-Flop and an inverter. The output of the D Flip-Flop switches every two clock cycle by using the feedback inverter. The character of this DLL architecture is the hierarchical delay line. So the comparator must be divided to coarse delay comparator and fine delay comparator, respectively. In next sections, the functions of every block will be explained.

4.3.1 Delay Line

The delay line of modified DLL architecture includes coarse delay and fine delay for the hierarchical architecture. The delay line of fine delay will be discussed in section 4.3.4 for explaining more clearly. In this section, the delay line of coarse delay is the main subject. The coarse delay line receives the signal from fine delay line. The

basic stage of coarse delay is combined by inverter chains and capacitance. The schematic of the basic stage of coarse delay is shown in Fig. 4.4. The delay time of every stage is 900 ps, and every stage is divided to 6 minor stages. It is because that the largest delay time of fine delay is 150ps. For hierarchical delay line, it is significant that the difference between the largest fine delay time and the smallest coarse delay time must be reduced for decreasing the jitter cased by the discontinuous delay. The capacitances are applied to fit the delay time. For power consumption consideration, every stage applies a NAND gate to control whether the stage should be operated or not. If there is no NAND gate in the coarse delay line, the whole coarse delay line will always be operated. The long coarse delay line will have large power consumption. So the NAND gate can turn off the unnecessary coarse delay line to reduce the power consumption.

4.3.2 Shifter

In conventional DLL architecture, the up/down counter often applies adder to realize the function. But the delay lines are often controlled by thermal meter code.

The decoder is required to decode the signal of up/down counter. To spare the complexity of the control circuit, the modified DLL architecture applies the shifter, shown in Fig. 4.5, to replace the up/down counter and decoder. Every bit of the shifter has the functions of shift left, shift right, and not shift. The command of shift left means increasing delay time, and the input is connected to the lower bit. Contrarily, shift right means decreasing delay time, and the input is connected to the higher bit.

So the input of the LSB shift left is connected to Vdd. The input of the MSB shift right is connected to GND. This shifter can created the thermal meter code directly, and the code can be applied to control the delay line by using simple logic gates

transforming the code. This method can reduce the chip area efficiently.

4.3.3 Coarse Delay Comparator

The coarse delay comparator compares the value of divided internal clock, divided internal clock with 150ps delay, and divided internal clock with 900ps delay at the rising edge of the divided external clock. These delay times are decided by the one coarse delay stage delay time and the minor coarse delay stage delay time. All cases of the coarse delay comparator state are shown in Fig. 4.6. There are three bits signal that should be judged at the rising edge of the divided external clock. This can be realized by a D Flip-Flop that the control clock is connected to divided external clock. These cases can mainly be codified four parts, so the decoder is applied to decode these cases into two bits signal, reference the Table 4.1. The relationship between the function and the decoded signal is shown in this table clearly. It is simpler that codifying these cases into two bits signal. This can reduce the complexity of realizing the finite state machine (FSM) of the coarse delay control circuit. The operation theory of this FSM will be discussed in section 4.3.5 more detail.

4.3.4 Fine Delay Comparator and Fine Delay Operation Theory

The fine delay architecture is referenced [8]. This architecture adjusts the internal clock every two clock cycles. The block diagram is shown in Fig 4.7. The architecture equips two suites of the same adjusting equipment. Because each of the adjusting equipment adjusts one clock cycle of internal clock every two clock cycle. The comparator, shown in Fig 4.8, compares the crossing point of external clock and feedback clock. When feedback clock, ret. CLK-F, is at low logic level, the nodes, N1

and N2, are pulled up to the supply voltage that makes the signals, Up-F and Down-F, are at low logic level. When feedback clock, ret. CLK-F, is at high logic level, the comparator applies the inverter chain to make a short window that both ret. CLK-F and ret. CLK-Db are at high logic level. In this period of short window, the comparator compares the crossing point of the external clock, ext. CLK and ext.

CLKb. If the crossing point of external clock is faster than the feedback clock, the nodes N1 is higher than N2. The cross-coupled architecture, T4 and T5, will amplify the voltage difference between N1 and N2. The Up-F will be at the high logic level to create the delay time of the fine delay, and Down-F will be at the low logic level.

Also this architecture applies the dummy unit coarse delay (UCD) and replica unit coarse delay (UCD) to keep the continuation between fine delay time and coarse delay time. The signals, ϕmf and ϕmd, control the delay line of fine delay, in Fig. 4.9, whether it should be turned on or not. Fig. 4.9 shows the timing diagram of this fine delay operation. In cycle-1 and cycle-2 one of these two suites adjusting equipments is operated respectively. During cycle-1, the signal, ϕmf, turns on the fingers which are determined by the decoder to discharge the voltage of the node ϕmix. After unit coarse delay time, the signal, ϕmd, will turn on all fingers of the fine delay circuit until tm the beginning of the hold time, thold. Due to the different speed of discharging the node ϕmix, the node ϕmix has different hold voltage. At tin, all fingers are turned on to discharge the node ϕmix. Due to the different hold voltage, the node ϕout1 has different delay time during cycle-2. In this moment, another suite of fine delay control circuit is operated to discharge another suite of fine delay circuit. The output of the fine delay line connected to the input of the coarse delay line is applied the OR gate combining ϕout1 and ϕout2 which is the output of these two suites of fine delay circuit.

4.3.5 Finite State Machine

The finite state machine (FSM) controls the operation of coarse delay. It is mainly divided into two parts which control different delay time of the coarse delay.

The input of these finite state machines is made by decoding three signals, divided feedback clock, divided feedback clock with 150 ps delay, and divided feedback clock with 900 ps delay. This is explained in section 4.3.3, and the decoded signals are shown in Table 4.1. The finite state machine called FSM1 that controls 900 ps delay is shown in Fig. 4.10. When starting the DLL architecture the architecture adjusts internal clock by the order of 900 ps. After resetting or starting the circuit, FSM1 is at the state S0. In this state the delay time is the shortest, so if it receives “00”, the delay line should delay 900 ps not forward 900 ps. The output signals of FSM1 control the shifter. When the left bit is “1”, the shifter doesn’t shift whether the right bit is “1” or not. When the left bit is “0”, the shifter will shift left which means increasing delay time when the right bit is “1” and shift right oppositely.

Before FSM1 is at the state S2 that means the difference between internal clock and external clock is less than 900 ps, the finite state machine called FSM2 that controls 150 ps delay is at the state S0 in Fig. 4.11. Before FSM1 finishes its operation, the right bit of output signals is “1” to reset the data of FSM2 preventing the controlling error. The left and middle bit of output signals are the same as the output signals of FSM1. When FSM2 is at state S2, the locking signal becomes “1” to hold the data of these shifters and transfers the signal to the fine delay control circuits to start these fine delay control circuits. In this moment, the difference between external clock and internal clock is less than 150 ps.

4.4 DLLSIMULATION RESULT

Fig. 4.12 and Fig. 4.13 show the timing diagrams of DLL operating at 250 MHz and 66 MHz respectively. This DLL architecture equips signals to detect the delay adjustment. Also the DLL has a lock signal to announce the internal clock locked.

Figs. 4.14, 4.15, and 4.16 show the jitter histogram of DLL operated at 250 MHz with different corner and temperature, and the jitter are 33 ps, 42 ps, and 50 ps respectively.

Figs. 4.17, 4.18, and 4.19 show the jitter histogram of DLL operated at 66 MHz with different corner and temperature, and the jitter are 68 ps, 70 ps, and 80 ps respectively.

These figures show the jitter simulation influenced by different situation. The jitter of DLL operated at 66MHz is larger than at 250 MHz. This is because that the capacitances applied in this architecture are MOS capacitances. MOS capacitance is sensitive to operation voltage. The clock of DLL operated at 66 MHz passes through longer delay line so that it applies more MOS capacitances for delaying longer. Fig.

4.20 is the jitter histogram of DLL operated at 66 MHz with ideal capacitances, and the value of jitter is 50 ps.

4.5 CONCLUSION

Table 4.2 is the electric characteristics of this DLL architecture operated at different frequency. This DLL architecture has advantages of low current consumption and fast locking the internal clock. It can be operated at the frequency of 66 MHz to 250 MHz. But the coarse delay line of this architecture can be improved for decrease the jitter. If this architecture can overcome this disadvantage, it can be realized better performance in DDR SDRAM applications.

Table 4.1

Function and Decode of Coarse Delay State

State Function Decode

Fig. 4.1 Block Diagram of DLL Architecture

Fig. 4.2 Block Diagram of Modified DLL Architecture

Fig. 4.3 Schematic of Divider

Fig. 4.4 Basic Stage of Coarse Delay

Fig. 4.5 Schematic of Shifter

Fig. 4.6 Waveform of Coarse Delay Cases

Fig. 4.7 Block Diagram of Fine Delay Control Circuit

Fig. 4.8 Schematic of Fine Delay Comparator

Fig. 4.9 Schematic and Timing Diagram of Fine Delay

Fig. 4.10 Finite State Machine of 900 ps Adjustment

Fig. 4.11 Finite State Machine of 150 ps Adjustment

Fig. 4.12 Timing Diagram of DLL at 250 MHz

Fig. 4.13 Timing Diagram of DLL at 66 MHz

Fig. 4.14 Jitter Simulation of DLL at 250 MHz in TT Corner 25℃

Fig. 4.15 Jitter Simulation of DLL at 250 MHz in FF Corner 85℃

Fig. 4.16 Jitter Simulation of DLL at 250 MHz in SS Corner 0℃

Fig. 4.17 Jitter Simulation of DLL at 66 MHz in TT Corner 25℃

Fig. 4.18 Jitter Simulation of DLL at 66 MHz in FF Corner 85℃

Fig. 4.19 Jitter Simulation of DLL at 66 MHz in SS Corner 0℃

Fig. 4.20 Jitter Simulation of DLL at 66 MHz in TT Corner 25℃ Font Type

Chapter 5

Summary and Future Works

5.1 SUMMARY

Chapter 2 introduces the specifications of SSTL_2 I/O circuit and DLL. This chapter clearly discusses AC and DC specifications of the SSTL_2 standard. It also simply introduces the background for the SSTL_2 and DLL architecture in DDR SDRAM applications.

Chapter 3 presents the SSTL_2 architecture in different methods. SSTL_2 I/O circuits are fabricated in 0.13 μm 1P8M CMOS process and the power supplies are 2.5 V and 1.2 V. The maximum operation frequency of SSTL_2 without slew rate control circuit is 500 Mbps (250 MHz clock rate) for operating 3 bits applied on the same power line. SSTL_2 with slew rate control circuit improves the disadvantage of the first version. It can be operated at the speed of 600 Mbps for 8 bits on the same power line. Although the maximum operation frequency of SSTL_2 is 400 Mbps, the higher operation speed SSTL_2 architecture can achieve the more margin it can sustain.

Chapter 4 discusses the DLL architecture design. This DLL architecture can be operated at the range of 66 MHz to 250 MHz. This DLL architecture applies hierarchical delay line architecture to adjust the internal clock. The hierarchical delay line architecture must notice the continuance between fine delay time and coarse delay time. The maximum jitter is 80 ps which arise in the case of operating the DLL architecture at the operation frequency of 250 MHz in 0℃.

5.2 FUTURE WORKS

Although SSTL_2 is verified to be operated normally in the DDR SDRAM applications, it can be improved to get better performance. It can be applied more I/O circuits operating on the same power line to reduce power lines routing in the chip.

The DLL architecture can improve the disadvantage of coarse delay line to reduce the

The DLL architecture can improve the disadvantage of coarse delay line to reduce the