e1
y1 NCF1
NCF2
e1 e2
y2 x 1st y
Filter Loop
2nd Loop Filter
Figure 1.1: Traditional dual-stage∆Σ modulator structure.
required opamp unity-gain frequency is about 5fs = 6.4 GHz. It is difficult for an opamp with such a speed to have a decent dc gain.
There are calibration techniques that can improve the frequency accuracy of the noise-shaping functions of the DSMs [10–13]. They all assume that the opamps have sufficiently large dc gain. There are DSM calibration techniques that try to correct the errors caused by non-ideal integrators that exhibit integration leakage as well as distortion [14, 15].
However, the required processing circuits are cumbersome.
The accuracy requirement for the SC integrators can be relaxed by increasing the order of the DSM loop, or by employing the multi-stage noise-shaping (MASH) structure [16–19]. A higher-order DSM may require more quantization levels from its internal analog-to-digital converter (ADC) and digital-to-analog (DAC) to stabilize the loop [20], yielding complex circuits. Thus a cascaded DSM which can avoid stability problem is relatively attractive.
A conventional dual-stage cascaded DSM is shown in Figure 1.1. There are two DSMs followed by the responsing noise cancellation filter (NCF). Idealistically, NCFs eliminate the first stage quantization noise completely, and shape the second stage quantization noise once more. However, the mismatch between analog loop filter and digital cancella-tion filter is unavoidable. This leads the first stage quantizacancella-tion noise leaks into the signal bandwidth and degrades the overall SQNR of DSM. Too often, the quantization noise
fs
fs
DAC DAC
sub−ADC
f[k]
x(t) x[k] y[k]
sub−ADC
x(t) y[k]
f(t) H(s)
H(z)
Figure 1.2: Continuous-time∆Σ modulator and discrete-time ∆Σ modulator.
leakage is the major cause in the drop of DSM performance. This undesired effect typi-cally requires high accuracy analog components to lessen. Circuit level techniques used to enhance the accuracy of SC integrators can also be applied to improve qualities of analog loop filter. Similarly, all lead analog loop filters of slow speed and large power consump-tion. Thus the feasibility of cascaded DSMs with the advanced CMOS technologies is limited.
There is an alternative cascaded DSM structure, sturdy MASH [21], can mitigate the matching requirements [21]. Although the demand on DAC performance gets more press-ing. Using the adaptive NCF to alleviate the noise leakage in background are devel-oped [22, 23]. However, it is difficult to obtain the required parameters from the DSM digital output alone.
Comparing to DT DSMs, the continuous-time (CT) DSMs can use opamps of less speed [24–29]. However, the time constant of a CT integrator is not as robust as that of a DT integrator. This disadvantage will become even more pronounced as technology will scale further [30]. Time-constant calibration is required in most CT DSM designs. In
1.3. CONTRIBUTIONS 5
addition, the excess loop delay in a CT DSM requires compensation to avoid instability or the degradation of the in-band noise suppression. This compensation needs to cover the PVT variations. The internal DACs in the CT DSMs are crucial. In additional to the static conversion errors, the jitter and dynamic distortion of those DACs also degrade the DSM performance. More quantization levels for the DAC may be needed. Those DACs may require calibration [29]. The CT DSMs are more sensitive to the clock jitter, especially when the OSR is low [31].
1.3 Contributions
To take advantage of advanced nano-scale CMOS technologies, this thesis proposes the use of opamps with a simple circuit configuration and minimum-length MOSFETs.
The resulting SC integrators are high-speed and low-power but they are also lossy. A background calibration is then carried out to compensate for the integration leakage of the integrator and recover the noise-shaping capability of the DSM.
Moreover, to achieve wide bandwidth and large dynamic range for a cascaded DSM, this thesis proposes the use of combing low-complexity circuits and digital calibrations.
The resulting analog loop filters are high-speed and low-power but also inaccurate. Two different types of digital calibrations are applied. We first employ the integrator leakage calibration to correct the poles of the integrators. We then use the noise leakage calibra-tion to minimize the quantizacalibra-tion noise from the first loop leaking to the DSM combined output. As a result, the cascaded DSM preforms higher-order noise shaping and SQNR is restored. And the noise leakage calibration can relaxe the component matching require-ments of the cascaded DSMs.
Since each calibration adjusts only one parameter, it is robust. All calibrations can proceed in the background without interrupting the normal DSM operation. The calibra-tion processors are simple digital circuits. They do not include any complex filter. A 2-2 cascaded DSM was fabricated using a 65 nm CMOS technology to verify our scheme. It has a sampling rate of 1.1 GHz and an input bandwidth of 16.67 MHz with an oversam-pling ratio (OSR) of 33. The measured signal-to-noise-and-distortion ratio (SNDR) and dynamic range (DR) are 74.32 dB and 81 dB respectively. The chip consumes 94 mW
from a 1 V supply.
1.4 Organization
This thesis is organized as follows. Chapter 2 discusses the integration leakage of DSMs, and introduces the integrator leakage calibration. Various design cases and its de-sign consideration are included. Chapter 3 discusses the noise leakage of cascaded DSMs, and introduces the noise leakage calibration. A 2-2 cascaded DSM are instantiated for demonstration. Chapter 4 illustrates a 81 dB dynamic range 16.67MHz bandwidth DSM using the proposed calibration techniques. The circuits implementation and experimental results of this prototype are presented. Finally, conclusions and recommendations for fu-ture works will be given in Chapter 5. In addition, Appendix A provides a mathematical treatment of the AAR-based Calibration for DSMs.
Chapter 2
Integrator Leakage Calibration for DSMs
Switched-capacitor (SC) integrators realized with low-gain opamps are lossy. Lossy integrators in a delta-sigma modulator (DSM) degrade the signal-to-quantization-noise ratio (SQNR) of the DSM. In this chapter, we propose an integration-leakage calibration technique for the integrators in a SC DSM. To calibrate an integrator, its integration leak-age is detected in the digital domain, while the leakleak-age compensation is added to the same integrator in the analog domain. The leakage compensation signal path adds little noise and loading to the original integrator. To detect the integration leakage of an integrator, an out-of-band square wave is injected into the DSM, which can be easily removed by the decimation filter following the DSM. The integration-leakage detector is a simple digital circuit that performs the accumulation-and-reset (AAR) operation. The proposed scheme can calibrate all integrators in a DSM of any form. It calibrates one integrator at a time. It can proceed in the background without interrupting the normal DSM operation. Once all integrators are calibrated, the noise-shaping capability of the DSM is recovered, and the SQNR performance of the DSM is restored. Since each integrator is calibrated separately, the design parameters of the corresponding calibration signal and calibration processor (CP) can be easily optimized.
The rest of this paper is organized as follows. Section 2.1 discusses the effect of in-tegration leakage on the SQNR performance of DSMs. Section 2.2 introduces the SC
7
Cs
Figure 2.1: A conventional switched-capacitor (SC) integrator.
integrators with leakage compensation. Section 2.3 introduces the proposed calibration technique with a 1st-order DSM design case. Design considerations are outlined. Sec-tion 2.4 applies the calibraSec-tion technique to a 2nd-order DSM design case. SecSec-tion 2.5 applied the techniques to high-order DSMs. A 3rd-order DSM design case is demon-strated. Finally, Section 2.6 draws conclusions. In addition, the stochastic analysis of the calibration algorithm is addressed in Chapter A.