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Calibration Techniques for Discrete-Time
Delta-Sigma Modulators
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Student : Su-Hao Wu
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A Dissertation
Submitted to Department of Electronics Engineering
and Institute of Electronics
College of Electrical and Computer Engineering
National Chiao Tung University
in Partial Fulfillment of the Requirements
for the Degree of
Doctor of Philosophy
in
Electronics Engineering
July 2013
Hsinchu, Taiwan, Republic of China
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Calibration Techniques for Discrete-Time
Delta-Sigma Modulators
Student : Su-Hao Wu
Advisor : Jieh-Tsorng Wu
Department of Electronics Engineering
and Institute of Electronics
National Chiao Tung University
Abstract
This thesis presents background calibration techniques to reshape the capability of noise shaping of discrete-time (DT) Delta-Sigma modulators (DSMs). The calibration can operate in the background without interrupting the normal operation of the DSM. The proposed scheme relaxes the requirement of opamp DC gain in a DT DSM. and relaxes the matching requirement in a cascaded-DSM.
The opamp in a DT DSM is requested to sacrifice the DC gain for wide-band appli-cations. This induces the issue of integrator-leakage and a degraded signal-to-noise-and-distortion ratio (SNDR). We develops an integrator-leakage calibration technique for a DT DSM. In the calibration of an integrator, its integration leakage is determined in the digital domain, and the leakage compensation is applied to the same integrator in the ana-log domain. The proposed scheme can be used to calibrate all of the integrators in a DT DSM of any form. The developed scheme can relax the requirement of opamp DC gain in the high-speed high-resolution DT DSMs.
an noise-leakage calibration technique with low-complex circuits. The noise leakage is determined by injecting an out-of-band signal, and the leakage is eliminated by merely adjusting the gain of digital filter. The developed scheme can relax the matching require-ment in the cascaded DSMs and accomplish the higher-order noise shaping.
A 2-2 cascaded discrete-time DSM is fabricated in a 65 nm CMOS technology. Each stage of DSM consists of two integrators realized the low gain high speed opamp. The integrator leakage originated in the first stage is reduced by integrator leakage calibration at first. Then, the mismatch between the analog loop filter and the digital noise cancel-lation filter is cured by noise leakage calibration. The proposed calibrations enable the modulator to perform the high-speed high-resolution analog-to-digital conversion.
The active area of the fabricated DSM is 0.58 × 0.33 mm2. This cascaded DSM with open-loop opamp gain of 20 dB is operating at 1.1 GHz clock rate. Its OSR is 33 and its bandwidth is 16.67 MHz. The DSM consumes 94mW from 1.0 V power supply. Before activating the calibrations, the SNDR is 54 dB and the dynamic range (DR) is 60 dB. After activating the integrator leakage calibration and the noise leakage calibration, the SNDR becomes 74 dB and the DR becomes 81 dB. The figure-of-merit of the DSM is 163.5 dB.
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Contents
Z` i
English Abstract iii
* v
List of Tables xi
List of Figures xiii
1 Introduction 1
1.1 Motivation . . . 1
1.2 Design Challenges . . . 1
1.3 Contributions . . . 5
1.4 Organization . . . 6
2 Integrator Leakage Calibration for DSMs 7 2.1 Integration Leakage and Its Effect . . . 8
2.2 Integrator with Leakage Compensation . . . 13
2.3 First-Order DSM Design Case . . . 15
2.3.1 Design of c[k] and g[k] . . . 19
2.3.2 Design of Nthand ∆β . . . 21
2.3.3 Simulation Results . . . 23
2.4 Second-Order DSM Design Case . . . 25
2.5 High-Order DSM Design Case . . . 30 vii
2.6 Summary . . . 38
3 Noise Leakage Calibration for Cascaded DSMs 41 3.1 Noise leakage Issue . . . 41
3.2 A Design Case of 2-2 Cascaded DSM . . . 43
3.2.1 Integrator leakage Calibration . . . 47
3.2.2 Noise leakage Calibration . . . 51
4 A 81 dB DR 16.67 MHz BW Cascaded DSM 55 4.1 DSM Architecture . . . 56
4.1.1 Dithering . . . 59
4.1.2 Calibration of Integrator Leakage . . . 60
4.1.3 Calibration of Noise Leakage . . . 64
4.2 Circuit Design . . . 65
4.2.1 Operational Amplifiers . . . 65
4.2.2 Integrators . . . 66
4.2.3 Adder and DAC . . . 68
4.2.4 Comparator . . . 71
4.3 Chip Measurement . . . 75
4.3.1 Setup . . . 75
4.3.2 Experimental Results . . . 79
4.4 Summary . . . 83
5 Conclusions and Future Works 87 5.1 Conclusions . . . 87
5.2 Recommendations for Future Investigation . . . 88
Appendix A Stochastic Analysis of AAR-based Calibration 89 A.0.1 The First-Order DSM . . . 89
A.0.2 The Second-Order DSM . . . 95 viii
Bibliography 97
Vita 105
Publication List 106
List of Tables
1.1 Baseband requirements of ADCs for various wireless standards. . . 2
4.1 Integrator variations due to opamp dc gain A0. . . 56
4.2 Capacitor size of Integrators. . . 68
4.3 S-R latch operation. . . 74
4.4 Power and area of circuit blocks. . . 82
4.5 Comparison of wide-bandwidth DSMs. . . 84
List of Figures
1.1 Traditional dual-stage∆Σ modulator structure. . . . 3
1.2 Continuous-time∆Σ modulator and discrete-time ∆Σ modulator. . . . . 4
2.1 A conventional switched-capacitor (SC) integrator. . . 8
2.2 Integrator time-domain output response. Vi[k]= 0 for k > 0. . . . 9
2.3 A delta-sigma modulator with lossy integrators. . . 9
2.4 DSM SQNR enhancement versus β. OSR = 64. For a 1st-order DSM, M = 1. For a 2nd-order DSM, M = 2. For a 3rd-order DSM, M = 3. . . 12
2.5 DSM SQNR enhancement versus oversampling ratio (OSR). . . 13
2.6 Proposed switched-capacitor (SC) integrator with leakage compensation. 14 2.7 Proposed non-inverting switched-capacitor (SC) integrator with leakage compensation. . . 15
2.8 A 1st-order DSM with the proposed calibration scheme. . . 16
2.9 Transfer curve of sub-ADC and sub-DAC. . . 16
2.10 Calibration signal flow diagram. . . 17
2.11 Calibration signal waveforms. . . 18
2.12 Accumulation-and-reset (AAR) operation. . . 19
2.13 The transient response of d[k] with different β. . . 20
2.14 SQNR of the 1st-order DSM design case with different Vc. The opamp in the DSM is ideal. . . 21
2.15 σ(β) versus Nthwith different ∆β. . . 22
2.16 β[k] transient response of the 1st-order DSM design case. . . . 24
2.17 Output spectra of the 1st-order DSM design case. . . 24 xiii
2.20 Calibration signal flow diagram for β2calibration. . . 27
2.21 Output spectra of the 2nd-order DSM design case. . . 28
2.22 The amplitude of Vcjvs. peak SQNR as well as the magnitude of integra-tor output. . . 29
2.23 Calibration of a CIFB DSM. . . 30
2.24 c[k]-to-w[k] signal flow in a CIFB DSM. . . . 31
2.25 Calibration of a CIFF DSM. . . 32
2.26 c[k]-to-w[k] signal flow in a CIFF DSM. . . . 33
2.27 A 3rd-order DSM with the proposed calibration scheme. . . 34
2.28 Output spectra of the 3rd-order CIFB DSM design case. . . 35
2.29 Filtered output spectra of the 3rd-order DSM design case by a sinc4 deci-mation filter. . . 36
2.30 A 3rd-order CIFF DSM with local resonator feedback. . . . 37
2.31 Inverter-based opamp with common-mode feedback. . . 37
2.32 Output spectra of the 3rd-order CIFF DSM design case. . . . 39
3.1 Traditional dual-stage∆Σ modulator structure. . . 42
3.2 A 2-2∆Σ architecture with adaptive noise cancelantion fillter. . . 44
3.3 Proposed 2-2∆Σ architecture with leakage calibration. . . 45
3.4 Proposed 2-2∆Σ modulator with calibration techniques. . . 46
3.5 The first integrator calibration block diagram. . . 48
3.6 σ(β1) versus Nth1with different ∆β1. . . 50
3.7 Signal flow diagram of the second integrator calibration. . . 50
3.8 The noise leakage calibration block diagram. . . 52
4.1 A 4th-order MASH DSM with digital calibrations. . . 56
4.2 Effect of integrator pole β on the noises e1and e2in the DSM output. . . . 58
4.3 Autocorrelatoin of the first stage quantization noise. . . 60
4.4 Spectra of the first integrator output. . . 61
4.5 DSM SNDR versus input level at various Vc1values. . . 62
4.6 β1[k] transient response. . . . 63
4.7 The integrator-leakage calibration of the first loop in the DSM. . . 64
4.8 Operational amplifier schematic. . . 66
4.9 Common-mode feedback schematic. . . 67
4.10 Differential schematic of the first integrator. . . 67
4.11 Schematic of clock boosting. . . 68
4.12 Schematic of the first loop in the DSM and its timing scheme. . . 70
4.13 Schematic of Constant-Vgsboostrapped nMOSFET switch. . . 71
4.14 DWA rotator schematic. . . 72
4.15 DWA pointer and encoding. . . 72
4.16 Comparator preamplifier schematic. . . 73
4.17 DC gain versus differential output voltage. . . 74
4.18 Comparator latch schematic. . . 75
4.19 Propagation delay from the latch in the comparator to the DAC1 switches. 76 4.20 Modulator chip micrograph. . . 76
4.21 Photo of printed circuit board. . . 77
4.22 Measurement Setup. . . 78
4.23 Current-steering buffers. . . 79
4.24 Eye-diagram of output data. . . 80
4.25 Measured output spectra of the DSM. . . 81
4.26 Measured in-band output spectra of the DSM. . . 81
4.27 Measured dynamic performance of the DSM. . . 82
4.28 Comparison with various ADCs. . . 85
4.29 Comparison with various DSMs, whose bandwidth is above 10MHz. . . . 85
A.1 Representation of the AAR-based CP whithout reset. . . 90
A.2 The linear model of a DSM in cascade with an AAR-based CP. . . 90
A.3 Histogram of s[k = 512] with 1000 Monte Carlo simulations for a 4-bit 1st-order DSM. β = 0.99, V = ∆, fq = fs 16 and Dg = 25% . . . 93
A.4 Transient behaviors of PF, PD and PI when Nth = 16. β = 0.99, V = ∆, fq = fs 16 and Dg = 25%. . . 94
Chapter 1
Introduction
1.1
Motivation
The developments of anlog-to-digital converters (ADCs) are driven by the increas-ing demand for signal bandwidth and dynamic range in applications such as wireline and wireless communications, medical imaging and high-definition video processing. Several communication systems and multi-channel applications, such as digital FM and LTE-advanced, need medium resolution ADCs with bandwidths in the tens of MHz range. Table 1.1 lists the requirements of ADC in receivers for various mobile communication. To achieve high data rates, these applications rely on advanced digital modulation tech-niques that can be advantageously implemented in nanometer-CMOS, which motivates the development of suitable ADCs in these technologies. This combination of resolu-tion and bandwidth were considered the exclusive forte of pipelined ADCs. Delta-Sigma modulators (DSMs) are now being seen as attractive alternatives to pipelined converters in such applications.
1.2
Design Challenges
The noise-shaping function of a DSM can effectively suppress quantization noise when it is operated with oversampling, thus a DSM can achieve higher dynamic range than other ADC types. Oversampling ADCs that use DSMs require faster analog circuits
Specification Standard Bandwidth (MHz) Dynamic range (bits) WCDMA 3G Telecom 3.84,4 9-12
HSDPA 3.5G Telecom 5 9-13
Zigbee IEEE 802.15 5 12
HipeLAN European IEEE 802.11 6 14 Wifi IEEE 802.11, WLAN 11,20,22 8-14 WiMax IEEE 802.16, WMAN 5,10,20 7-11 LTE 3.9G Telecom 5,10,20 10-13 LTE-advanced 4G Telecom 20 12
Table 1.1: Baseband requirements of ADCs for various wireless standards.
than Nyquist-rate ADCs. Consider a discrete-time (DT) DSM that comprises a cascade of switched-capacitor (SC) integrators. Each integrator contains an opamp. The open-loop unity-gain frequency and slew rate of the opamp determine the speed of the integrator, while the dc voltage gain of the opamp dictates the quality of the integration function. Meanwhile, the integrator transfer function is also more sensitive to process-voltage-temperature (PVT) variations. An SC integrator realized with a low-gain opamp is lossy, meaning that it exhibits integrator-leakage. If the integrators in a DSM are lossy, then the noise-shaping capability of the DSM is weakened, degrading the signal-to-quantization-noise ratio (SQNR).
As CMOS technologies advance, MOSFETs become smaller and faster, but their in-trinsic voltage gain, gm/gds, also decreases. [1]. Consider a standard 32 nm CMOS. A
minimum-channel-length MOSFET has a maximum transit frequency ,fT, of over 400
GHz but it has an intrinsic gain gm/gds of only about six [2, 3].
Although some circuit level techniques have been proposed to raise the dc gain of opamps, such as multi-stage amplifiers [4], gain-compensated integrators [5,6], correlated double sampling [7, 8], and correlated level shifting [9]. These existing solutions can restore SNQR of DSMs, but may be inappropriate in deep-submicron technology since low intrinsic gain and limited supply headroom. Moreover, all sacrifice the speed.
The performance of a wide-band DT DSM is usually limited by its internal opamps that realize the integrator function. For an input bandwidth of 20 MHz and an over-sampling ratio (OSR) of 32, the corresponding over-sampling rate is fs = 1.28 GHz, and the
1.2. DESIGN CHALLENGES 3
e1
NCF1
y1
NCF2
e1
e2
y2
y
x
1st
Filter
Loop
2nd
Loop
Filter
Figure 1.1: Traditional dual-stage∆Σ modulator structure.
required opamp unity-gain frequency is about 5fs = 6.4 GHz. It is difficult for an opamp
with such a speed to have a decent dc gain.
There are calibration techniques that can improve the frequency accuracy of the noise-shaping functions of the DSMs [10–13]. They all assume that the opamps have sufficiently large dc gain. There are DSM calibration techniques that try to correct the errors caused by non-ideal integrators that exhibit integration leakage as well as distortion [14, 15]. However, the required processing circuits are cumbersome.
The accuracy requirement for the SC integrators can be relaxed by increasing the order of the DSM loop, or by employing the multi-stage noise-shaping (MASH) structure [16–19]. A higher-order DSM may require more quantization levels from its internal analog-to-digital converter (ADC) and digital-to-analog (DAC) to stabilize the loop [20], yielding complex circuits. Thus a cascaded DSM which can avoid stability problem is relatively attractive.
A conventional dual-stage cascaded DSM is shown in Figure 1.1. There are two DSMs followed by the responsing noise cancellation filter (NCF). Idealistically, NCFs eliminate the first stage quantization noise completely, and shape the second stage quantization noise once more. However, the mismatch between analog loop filter and digital cancella-tion filter is unavoidable. This leads the first stage quantizacancella-tion noise leaks into the signal bandwidth and degrades the overall SQNR of DSM. Too often, the quantization noise
fs fs DAC DAC sub−ADC f[k] x(t) x[k] y[k] sub−ADC x(t) y[k] f(t) H(s) H(z)
Figure 1.2: Continuous-time∆Σ modulator and discrete-time ∆Σ modulator. leakage is the major cause in the drop of DSM performance. This undesired effect typi-cally requires high accuracy analog components to lessen. Circuit level techniques used to enhance the accuracy of SC integrators can also be applied to improve qualities of analog loop filter. Similarly, all lead analog loop filters of slow speed and large power consump-tion. Thus the feasibility of cascaded DSMs with the advanced CMOS technologies is limited.
There is an alternative cascaded DSM structure, sturdy MASH [21], can mitigate the matching requirements [21]. Although the demand on DAC performance gets more press-ing. Using the adaptive NCF to alleviate the noise leakage in background are devel-oped [22, 23]. However, it is difficult to obtain the required parameters from the DSM digital output alone.
Comparing to DT DSMs, the continuous-time (CT) DSMs can use opamps of less speed [24–29]. However, the time constant of a CT integrator is not as robust as that of a DT integrator. This disadvantage will become even more pronounced as technology will scale further [30]. Time-constant calibration is required in most CT DSM designs. In
1.3. CONTRIBUTIONS 5 addition, the excess loop delay in a CT DSM requires compensation to avoid instability or the degradation of the in-band noise suppression. This compensation needs to cover the PVT variations. The internal DACs in the CT DSMs are crucial. In additional to the static conversion errors, the jitter and dynamic distortion of those DACs also degrade the DSM performance. More quantization levels for the DAC may be needed. Those DACs may require calibration [29]. The CT DSMs are more sensitive to the clock jitter, especially when the OSR is low [31].
1.3
Contributions
To take advantage of advanced nano-scale CMOS technologies, this thesis proposes the use of opamps with a simple circuit configuration and minimum-length MOSFETs. The resulting SC integrators are high-speed and low-power but they are also lossy. A background calibration is then carried out to compensate for the integration leakage of the integrator and recover the noise-shaping capability of the DSM.
Moreover, to achieve wide bandwidth and large dynamic range for a cascaded DSM, this thesis proposes the use of combing low-complexity circuits and digital calibrations. The resulting analog loop filters are high-speed and low-power but also inaccurate. Two different types of digital calibrations are applied. We first employ the integrator leakage calibration to correct the poles of the integrators. We then use the noise leakage calibra-tion to minimize the quantizacalibra-tion noise from the first loop leaking to the DSM combined output. As a result, the cascaded DSM preforms higher-order noise shaping and SQNR is restored. And the noise leakage calibration can relaxe the component matching require-ments of the cascaded DSMs.
Since each calibration adjusts only one parameter, it is robust. All calibrations can proceed in the background without interrupting the normal DSM operation. The calibra-tion processors are simple digital circuits. They do not include any complex filter. A 2-2 cascaded DSM was fabricated using a 65 nm CMOS technology to verify our scheme. It has a sampling rate of 1.1 GHz and an input bandwidth of 16.67 MHz with an oversam-pling ratio (OSR) of 33. The measured signal-to-noise-and-distortion ratio (SNDR) and dynamic range (DR) are 74.32 dB and 81 dB respectively. The chip consumes 94 mW
from a 1 V supply.
1.4
Organization
This thesis is organized as follows. Chapter 2 discusses the integration leakage of DSMs, and introduces the integrator leakage calibration. Various design cases and its de-sign consideration are included. Chapter 3 discusses the noise leakage of cascaded DSMs, and introduces the noise leakage calibration. A 2-2 cascaded DSM are instantiated for demonstration. Chapter 4 illustrates a 81 dB dynamic range 16.67MHz bandwidth DSM using the proposed calibration techniques. The circuits implementation and experimental results of this prototype are presented. Finally, conclusions and recommendations for fu-ture works will be given in Chapter 5. In addition, Appendix A provides a mathematical treatment of the AAR-based Calibration for DSMs.
Chapter 2
Integrator Leakage Calibration for
DSMs
Switched-capacitor (SC) integrators realized with low-gain opamps are lossy. Lossy integrators in a delta-sigma modulator (DSM) degrade the signal-to-quantization-noise ratio (SQNR) of the DSM. In this chapter, we propose an integration-leakage calibration technique for the integrators in a SC DSM. To calibrate an integrator, its integration leak-age is detected in the digital domain, while the leakleak-age compensation is added to the same integrator in the analog domain. The leakage compensation signal path adds little noise and loading to the original integrator. To detect the integration leakage of an integrator, an out-of-band square wave is injected into the DSM, which can be easily removed by the decimation filter following the DSM. The integration-leakage detector is a simple digital circuit that performs the accumulation-and-reset (AAR) operation. The proposed scheme can calibrate all integrators in a DSM of any form. It calibrates one integrator at a time. It can proceed in the background without interrupting the normal DSM operation. Once all integrators are calibrated, the noise-shaping capability of the DSM is recovered, and the SQNR performance of the DSM is restored. Since each integrator is calibrated separately, the design parameters of the corresponding calibration signal and calibration processor (CP) can be easily optimized.
The rest of this paper is organized as follows. Section 2.1 discusses the effect of in-tegration leakage on the SQNR performance of DSMs. Section 2.2 introduces the SC
Cs
Ci
Vo
Cp
Vi
1
1
2
2
Figure 2.1: A conventional switched-capacitor (SC) integrator.
integrators with leakage compensation. Section 2.3 introduces the proposed calibration technique with a 1st-order DSM design case. Design considerations are outlined. Sec-tion 2.4 applies the calibraSec-tion technique to a 2nd-order DSM design case. SecSec-tion 2.5 applied the techniques to high-order DSMs. A 3rd-order DSM design case is demon-strated. Finally, Section 2.6 draws conclusions. In addition, the stochastic analysis of the calibration algorithm is addressed in Chapter A.
2.1
Integration Leakage and Its E
ffect
Consider a conventional SC integrator shown in Figure 2.1. Its z-domain transfer function is H(z)= Vo(z) Vi(z) = α 1 − βz−1 (2.1) with α = −Cs Ci 1+ A1 0 · Ci+Cs+Cp Ci β = 1+ A1 0 · Ci+Cp Ci 1+ A1 0 · Ci+Cs+Cp Ci (2.2) where A0 is the dc voltage gain of the opamp and Cp is the total parasitic capacitance
associated with the negative terminal of the opamp. If the opamp is ideal with A0 = ∞,
then α = −Cs/Ci and β = 1. Figure 2.2 illustrates the integrator time-domain output
2.1. INTEGRATION LEAKAGE AND ITS EFFECT 9 Vo Vo [k] [k] β= 1 β< 1 k 5 0 1 2 3 4 6 7 8 k 5 0 1 2 3 4 6 7 8
Figure 2.2: Integrator time-domain output response. Vi[k]= 0 for k > 0.
1 z β2 α2 1 z 1 z α1 β1 DAC 1 x[k] y[k] sub−ADC 1
k >0. If β < 1, then the charge on capacitor Cileaks and Vo[k] decreases as k progresses.
An integrator with β < 1 is an lossy integrator.
Figure 2.3 shows a delta-sigma modulator (DSM) that employs the lossy integrators. Although the coefficient α for the integrator of Figure 2.1 is negative, the coefficients α1
and α2 in Figure 2.3 are positive for simplicity. Their polarities can be easily changed in
a fully differential circuit configuration. Assume the digital-to-analog converter (DAC) is ideal. The difference between the sampled analog input x[k] and DAC output is integrated by two lossy integrators and then quantized by a sub-ADC. The sub-ADC introduces quantization errors, e[k]. The sub-ADC digital output y[k] can be expressed as
Y(z)= STF(z) · X(z) + NTF(z) · E(z) (2.3) where STF(z) is the signal transfer function and NTF(z) is the noise transfer function. They are STF(z) = α1α2 D(z) NTF(z) = 1 − β1z−1 1 − β2z−1 D(z) (2.4) where D(z)= 1 + (α1α2+ α2− β1− β2) z−1+ β1(β2− α2) z−2 (2.5)
If the integrators are lossy, i.e., β1 < 1 and β2 < 1, then the zeros of the NTF deviate
from the unit circle in the z-plane, diminishing the the DSM’s ability of suppressing the sub-ADC quantization errors.
Consider a M-th order DSM with M lossy integrators. Its NTF is expressed as NTF= 1 − βz−1M (2.6) The β coefficients are assumed to be identical for simplicity. If the sub-ADC in the DSM has B-bit resolution, then the DSM’s maximum signal-to-quantization-noise ratio (SQNR) is
SQNR(dB)= 1.76 + 6.02 × B + SQNRNTF (2.7) SQNRNTFis the SQNR enhancement by the NTF.
2.1. INTEGRATION LEAKAGE AND ITS EFFECT 11 To derives the SQNR enhancement, SQNRNTF of (2.7). Let ω = 2πf/fs be the
normalized angular frequency, where fsis the sampling frequency. If the input bandwidth
is fB, then the normalized input bandwidth is ωb = 2πfB/fs = π/OSR, where OSR =
fs/(2fB) is the oversampling ratio. Assume the noise shaping function of a M-th-order
DSM is NTF(z)= 1 − βz−1M
. All zeros deviate from 1 to β. Assume the quantization noise introduced by the sub-ADC is white and has a total power of Pe. The total in-band
noise power after noise shaping is
Pe,sh = Pe 2π Z+ωb −ωb NTF(ejω) 2 dω (2.8)
If OSR π, then, for |ω| < ωb, cos(ω) ≈ 1 − ω2/2. Using the binomial theorem [32],
we have NTF(ejω) 2 = 1 + β2−2β cos(ω)M ≈ (1 − β)2+ βω2M ≈ M X n=0 M! n!(M − n)!(1 − β) 2nβM−n· ω2M−2n (2.9) and Z+ωb −ωb NTF(ejω) 2 dω = M X n=0 M! n!(M − n)!(1 − β) 2nβM−n ω2M−2n+1 2M − 2n+ 1 = ω2M+1 2M+ 1 M X n=0 M! n!(M − n)! 1 − β ω 2n βM−n 2M+ 1 2M − 2n+ 1 (2.10)
From (2.8) and (2.10), the SQNR enhancement by the NTF is SQNRNTF = Pe Pe,sh = 2M+ 1 θ · π2M ×OSR 2M+1 (2.11) where θ= M X n=0 M! n!(M − n)! (2M + 1)βM−n 2M − 2n+ 1 OSR(1 − β) π 2n (2.12)
0.90
0.95
1.00
1.05
1.10
β
40
50
60
70
80
90
100
110
SQNR
NTF(dB)
M=3
M=2
β=1
M=1
Figure 2.4: DSM SQNR enhancement versus β. OSR= 64. For a 1st-order DSM, M = 1. For a 2nd-order DSM, M = 2. For a 3rd-order DSM, M = 3.
Expressing (2.11) in decibel scale leads to (2.7). Reference to (2.12), in which θ is the ratio of in-band noise power with NTF = 1 − z−1M to the in-band noise power with NTF= 1 − βz−1M. If β = 1, then θ = 1. If β 6= 1, then θ > 1 and SQNRNTFdecreases.
If β = 1, each term of (2.12) is zero except n = 0, then θ = 1. If β 6= 1, then θ > 1, yielding larger in-band quantization noise power.
Figure 2.4 shows the effects of β on SQNRNTF when OSR = 64. Consider an ideal 3rd-order DSM with β = 1. It can offer a SQNRNTF of 105 dB. However, if β = 0.9, the
resulting SQNRNTFis degraded to 77 dB. Figure 2.5 shows the effects of β on SQNRNTF when OSR increases. For an ideal M-order DSM, the SQNRNTFis improved by 6M+3 dB when the OSR is doubled. If β < 1, then it becomes less effective for the DSM to improve SQNRNTF by increasing OSR. Although above conclusions are established on assuming that all NTF’s zeros are localed at β for simplicity, similar results are obtained even NTF’s zeros are separated.
2.2. INTEGRATOR WITH LEAKAGE COMPENSATION 13
4
8
16
32
64
128
Oversampling Ratio (OSR)
20
40
60
80
100
120
SQNR
NTF(dB)
Μ=3,β=1
Μ=2,β=1
Μ=3,β=0.9
Μ=2,β=0.9
21dB/octave
15dB/octave
Μ=1,β=0.9
Μ=1,β=1
9dB/octave
Figure 2.5: DSM SQNR enhancement versus oversampling ratio (OSR).
2.2
Integrator with Leakage Compensation
Consider the integrator shown in Figure 2.1 and its time-domain output response shown in Figure 2.2. If β < 1 for the integrator, its output loses an amount of ∆Vo =
(1 − β)Vo[k − 1], as clock progresses from cycle k − 1 to cycle k. The integrator is lossy
and exhibits integration leakage. Figure 2.6 shows the proposed SC integrator to compen-sate this leakage. The capacitor Cf is added to sample Vo. The sampled V0is added to the
integrator in the next clock cycle. If Cf has the right capacitance, the integrator becomes
lossless. Similar integrator can be found in [33], which is used to reduce idle-channel tones.
The z-domain transfer function of the proposed integrator is (2.1) with
β= 1+ Cf Ci + 1 A0 Ci+Cp Ci 1+ A1 0 Ci+Cs+Cf+Cp Ci (2.13) The proposed integrator requires a correct Cf to make β = 1. Regardless of Cp, to make
Cs
Vo
Cp
Vi
1
Ci
Cf
1
1
2
2
2
Figure 2.6: Proposed switched-capacitor (SC) integrator with leakage compensation.
β= 1, we want
Cf =
Cs
A0−1
(2.14) Comparing to Cs, Cfis relatively small. The Cfcapacitor itself and its associated switches
add minuscule loading and noise to the integrator.
Figure 2.7 shows the proposed non-inverting SC integrator with integration leakage compensation. Its β can also be expressed as (2.13).
Both the integrators of Figure 2.6 and Figure 2.7 require constant calibration to adjust
Cf against process-voltage-temperature (PVT) variations. In our proposed scheme, Cf is
controlled by a digital signal T [k] ∈ {0, ±1, ±2, · · · }, such that
Cf = Cf0+ ∆Cf× T[k] (2.15)
where ∆Cf is the Cf digital control step size and Cf0is the Cf capacitance when T [k]=
0. The corresponding β is β = β0+ ∆β × T [k] (2.16) where ∆β ≈ 1+ A1 0 Cs+Cp Ci 1+ A2 0 Ci+Cs+Cf0+Cp Ci × ∆Cf Ci (2.17) In our calibration scheme, ∆β determines how close the β can be adjusted to approach 1. Referring to Figure 2.4, smaller ∆β makes β closer to 1, resulting in better SQNRNTF.
2.3. FIRST-ORDER DSM DESIGN CASE 15
Cs
Vo
Cp
Vi
1
2
Ci
Cf
2
2
1
1
Figure 2.7: Proposed non-inverting switched-capacitor (SC) integrator with leakage com-pensation.
2.3
First-Order DSM Design Case
Figure 2.8 shows a 1st-order DSM using the integrator of Figure 2.6. The integrator’s transfer function is expressed as (2.1). Although the integrator shown in Figure 2.6 has a negative α coefficient. The α coefficient in Figure 2.8 is positive. If Cs = Ciand A0 = 8,
then α = 0.8 and β = 0.9. This DSM includes a background calibration mechanism that automatically adjusts the Cf capacitor in the integrator to maximize SQNR.
In Figure 2.8, the sub-DAC has N levels and covers an output range of ±1. The least-significant-bit (LSB) size is
∆= 2
N −1 (2.18)
The DSM output is y[k]. If N is odd, y[k] has its value among {0, ±1, ±2, · · · , ±(N − 1)/2}. If N is even, y[k] has its value among {±0.5, ±1.5, · · · , ±(N/2 − 0.5)}, The DAC output is Vda[k] = ∆ × y[k − 1]. We assume the sub-ADC is a flash ADC, whose
input thresholds correspond to the middle of adjacent DAC outputs. There are N − 1 sub-ADC thresholds. The sub-sub-ADC LSB size is the same as (2.18). If the sub-sub-ADC is ideal, its input range is ±(1+ ∆/2). The quantization errors e[k] introduced by the sub-ADC have values between −∆/2 and+∆/2. The transfer curve of sub-ADC and sub-DAC are sketch in Figure 2.9.
Vc
1
z
Σ
| |>Nth
Σ
Vda
1
z
α
β
g[k]
c[k]=q[k]
[k]
sub−ADC
1
r[k]
s[k]
ACC1
BPD
ACC2
b[k]
T[k]
reset
Calibration Processor (CP)
x[k]
y[k]
DAC
Figure 2.8: A 1st-order DSM with the proposed calibration scheme.
Di Ai Di Di Aj Di Aj Aj Di Ai Di Aj Ai Ai DAC = x ∆ = x ∆ 0.5∆ 0.5∆ 1.5∆ 1.5∆ (N−1) 2 −(N−1) 2 −(N−1) 2 (N−1) 2 DAC −(N−2) 2 ∆ ∆ −∆ ∆ 2∆ (N−2)2 ∆ −(N−2)2 ∆ (N−2)2 ∆ N is even. 1 −2 N is odd. 2 0.5 1.5 1.5 2
2.3. FIRST-ORDER DSM DESIGN CASE 17
Σ
g[k] STF1 NTF1 NTF1 1 BPD y[k] d[k] x[k] e[k] c[k] r[k] ACC1 AAR reset s[k] b[k]Figure 2.10: Calibration signal flow diagram.
The DSM has a sampling rate of fs and a signal bandwidth of fB. Its over-sampling
ratio is OSR= fs/(2fB). The modulator digital output y[k] is
∆ × Y (z) = STF1(z) · X(z)+ NTF1(z) · E(z) (2.19) where STF1(z)= H(z) 1+ z−1H(z) NTF1(z) = 1 1+ z−1H(z) (2.20)
and H (z) is the transfer function of the integrator expressed in (2.1). As proposed in Section 2.2, the β of the integrator is adjustable. It is adjusted automatically by the cal-ibration processor (CP) shown in Figure 2.8. To facilitate calcal-ibration, a periodic square wave c[k] = q[k] × Vc is added to the sub-ADC input. The CP detects the calibrating
signal embedded in y[k], generates a control signal T [k], and adjusts β to approximate β to 1.
Figure 2.10 shows a signal flow diagram of the calibration. The modulator input x[k] and sub-ADC quantization errors e[k] are shaped by STF1 and NTF1 respectively. The
calibrating signal c[k] is shaped by NTF1, yielding d[k]. The summation of the above
three signals is converted to y[k] with a conversion gain of 1/∆. The calibrating signal
c[k] is expressed as a periodic binary square wave q[k] ∈ {−1,+1} multiplied by an amplitude of Vc. Thus, embedded in y[k], d[k] is the step response of NTF1triggered by
c[k]. Figure 2.11 shows the d[k] waveform. The step response has an initial value of
Vci = Vc×
2α+ 1 − β
α+ 1 − β (2.21)
It settles toward a final value of
Vcf = Vc×
1 − β
Vcf Vc −Vc −Vcf 1 1 1 1 k 0 q[k] k k 0 0 d[k] g[k] k 0 c[k]
Figure 2.11: Calibration signal waveforms. Since Vcf is proportional to 1 − β, it is used to detect β.
Figure 2.10 also shows the CP operation. The CP correlates the DSM output y[k] with a triple-valued sequence g[k] ∈ {−1, 0,+1}. The g[k] waveform is illustrated in Figure 2.11. It has the same polarity as q[k], but its value is set to 0 during the initial transition phase of d[k]. Thus, the resulting product r[k] contains only the valid Vcf
information. Following r[k] is an accumulator (ACC1) followed by a binary peak detector (BPD). Together they perform the accumulation-and-reset (AAR) operation [34, 35] to extract Vcffrom r[k] while removing the perturbations caused by x[k] and e[k]. The AAR
operation is described as follows. Accumulator ACC1 accumulates the r[k] sequence. Its output s[k] is monitored by a BPD with a threshold Nth > 0. Whenever s[k] reaches
either+Nth or −Nth, the BPD issues an output b[k] = +1 or b[k] = −1 for one clock
cycle respectively and reset s[k] to 0. The BPD output b[k] remains at 0 when no reset occurs. The BPD output b[k] is an estimate of the 1 − β polarity. The CP uses it to adjust the β of the integrator. As shown in Figure 2.8, following b[k] is another accumulator, ACC2, that accumulates the b[k] sequence. Its output T [k] controls the β according to (2.16).
Figure 2.12 illustrates the time-domain waveform of the ACC1 output s, and the wave-form of the resulting β. When β approaches 1, both |1 − β| and Vcf become smaller, and
2.3. FIRST-ORDER DSM DESIGN CASE 19 Nth1 Nth1 [k] β1 k k 0 s[k] 1
Figure 2.12: Accumulation-and-reset (AAR) operation.
The calibration has five design parameters, including the c[k] amplitude Vc, the c[k]
frequency fq, the g[k] duty ratio Dg, the BPD threshold Nth, and the T [k] control step
size ∆β. Referring to Figure 2.11, the duty ratio Dg is defined as the ratio of the time for
g[k] = +1 to the time for q[k] = +1. The duty ratio for g[k] = −1 and q[k] = −1 is assumed to be the same as Dg.
In the following subsections, we use the aforementioned 1st-order DSM design case to illustrate the design considerations for the proposed calibration scheme. The DSM block diagram is shown in Figure 2.8. Its sub-ADC and DAC have N = 16 quantization steps. The corresponding quantization step size is ∆= 2/(N − 1). It has a sampling frequency of fs and a corresponding sampling period of Ts = 1/fs. The integrator in Figure 2.8
is realized using the SC integrator of Figure 2.6 with a transfer function of (2.1). If the opamp has a dc gain of A0 = 8, then α = 0.8 and β = 0.9. Assume the DSM is used
with an over-sampling ratio of OSR = 64. The theoretical maximum SQNR is 74 dB if
A0 = ∞. We will apply the proposed calibration to recover SQNR.
2.3.1
Design of c[k] and g[k]
2 3 4 5 6 7 8 9 10
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0
1
2
3
4
5
6
7
8
9
10
k
0.0
0.5
1.0
1.5
2.0
d[k]
β=0.90
β=0.95
β=1.10
β=1.00
β=1.05
Figure 2.13: The transient response of d[k] with different β.
sub-ADC input. Let c[k] have a frequency of fq, a corresponding period of Tq = 1/fq,
and a duty cycle of 50%. The resulting d[k], as shown in Figure 2.11, is embedded in the sub-ADC output y[k]. In each fq cycle, the transient response of d[k] is a step response
of NTF1triggered by c[k]. It can be expressed as
d[k]= Vc×
2α(β − α)k + (1 − β)
α + 1 − β (2.23)
This step response has an initial value of Vci of (2.21) and then settles toward the Vcf of
(2.22). Figure 2.13 shows several d[k] waveforms with different β. The d[k] waveforms have settled near Vcf for k > 5. We choose Tq = 16Tsand Dg = 1/4, so that, in each d[k]
transient, d[k] has a period of 6 clock cycles to settle before g[k] is activated for 2 clock cycles. The frequency of the inject signal c[k] is fq = fs/16. As long as OSR > 8, the
frequency components of d[k] in y[k] is outside the signal band. It can be easily removed by the decimation filter following the DSM.
The injection of the calibration signal c[k] degrades the DSM’s maximum SQNR, since c[k] increases the signal range of the signal at the sub-ADC input. The SQNR degradation is a function of the c[k] amplitude Vc. Figure 2.14 shows the simulated SQNR
2.3. FIRST-ORDER DSM DESIGN CASE 21
-15
-10
-5
0
Input Amplitude (dBFS)
40
45
50
55
60
65
70
75
80
SQNR (dB)
Before Cal.
V
c= ∆
V
c=0
V
5∆
3∆
c=
V
c=
4dB
15dB
Figure 2.14: SQNR of the 1st-order DSM design case with different Vc. The opamp in the
DSM is ideal.
of the DSM design case. Its internal integrator is assumed to be ideal with α = 1 and
β = 1. The injected c[k] has a frequency fq = fs/16. In Figure 2.14, SQNR is plotted
against x[k] input amplitude at different Vc. The x[k] frequency is fin = (41/216)fs. If
Vc = 1∆ = 2/15, the maximum SQNR is 71 dB at −1.5 dBFS. If Vc = 3∆ = 6/15, the
maximum SQNR is 67 dB at −4.5 dBFS. If Vc = 5∆ = 10/15, the maximum SQNR is
66 dB at −4.5 dBFS. In this design example, we choose Vc= 1∆.
2.3.2
Design of N
thand ∆β
Figure 2.12 illustrates the transient response of β1 during the calibration. Consider
the DSM shown in Figure 2.8. The averaged variation of s[k] for one clock cycle is
∆s= DgVcf/∆. It takes Nth/∆scycles for s[k] to accumulate from 0 to+Nth (or −Nth)
so that T [k] is changed by 1 and β is changed by ∆β. Thus, we have
dβ dk = ∆β Nth/∆s = ∆βDgVc Nth∆ 1 − β 1 − β+ α ≈ ∆βDgVc Nth∆α (1 − β) (2.24)
0
8
16
24
32
40
48
56
64
N
th0
4 m
8 m
12 m
16 m
20 m
24 m
σ(β)
∆β=0.02
∆β=0.01
∆β=0.03
Figure 2.15: σ(β) versus Nthwith different ∆β.
The calibration loop can be modeled as a single-pole feedback system. The transient response of β can be expressed as
β[k]= 1 − (1 − β[0]) × e−k/τ (2.25) The time constant τ is
τ = Nth Dg · ∆ Vc · α ∆β (2.26)
From (2.26), a smaller Nth and a larger ∆β lead to a smaller τ, yielding a faster
calibration speed. However, as the calibration process converges, the behavior of β[k] becomes a discrete random fluctuation around 1 [34]. Referring to Figure 2.10, both x[k] and e[k] induce this fluctuation. Their effects are diminished by the AAR operation. A larger Nth and a smaller ∆β lead to a smaller fluctuation in β, yielding the better SNDR
performance for the DSM.
Figure 2.15 shows the standard deviation of the β[k] fluctuation from the system sim-ulation of the DSM design case. The standard deviation σ(β) increases drastically for
2.3. FIRST-ORDER DSM DESIGN CASE 23
Nth < 8. As Nthincreases, the standard deviation of β fluctuation, σ(β), converges to an
averaged value.
When the H1 calibration process converges, the behavior of β1 becomes a discrete
random fluctuation around 1. If Nth = ∞, β1 alternates between only two values, which
are βa = 1 − x∆β and βb = 1 + (1 − x)∆β, where 0 ≤ x ≤ 1 depending on β0. Define
the probability for β = βaas Pa, and the probability for β = βbas Pb. Since the expected
value of β is 1, i.e., βaPa+ βbPb= 1, we have Pa = 1 − x and Pb = x. If x is given, define
the standard deviation of β1as
σ(β[x])=p(βa−1)2Pa+ (βb−1)2Pb= ∆β
p
x(1 − x) (2.27) If x is uniformly distributed from 0 to 1, the standard deviation of β is
σ(β)= s Z1 0 σ(β[x])2dx= ∆β√ 6 = 0.408 × ∆β (2.28) Chapter A contains a more detail of the above equation.
From Figure 2.4 and seeking the loss of SQNRNTFby less than 1 dB, we want 3σ(β) < 0.015, yielding ∆β < 0.0122. In this design case, we choose ∆β= 0.01 and Nth = 24.
2.3.3
Simulation Results
This 1st-order DSM design case is verified by using time-domain simulation. Cal-ibration design parameters are fq = fs/16, Dg = 0.25, Vc = 1∆, ∆β = 0.01, and
Nth = 24. The resulting time constant τ = 7680. Figure 2.16 shows the calibration
transient response. The solid line is the β[k] transient response from simulation and the smooth dashed line is the calculation using (2.25). It takes a calibration time of 3τ for β to converge from 0.9 to 0.995, where the SQNR degradation due to a non-ideal β is less than 1 dB. Assume the DSM input bandwidth is 2 MHz and the sampling frequency is
fs = 256 MHz, yielding an oversampling ratio OSR = 64. Then a calibration time of 3τ
is 0.09 msec. Figure 2.17 shows the DSM output spectra before and after calibration. The input is a sine wave with a frequency of (41/216)fs and an amplitude of −2 dBFS. The
resulting SQNR is 58 dB before calibration, and is improved to 70 dB after calibration. The frequency components of c[k] are visible in Figure 2.17. They are far away from the signal band.
0
20000
40000
60000
80000
k
0.9
0.92
0.94
0.96
0.98
1
β
Simulation
Calculation
Figure 2.16: β[k] transient response of the 1st-order DSM design case.
2.4. SECOND-ORDER DSM DESIGN CASE 25 w[k] 2 c 1 c 1 T T1 1 z Vda 2 T 1 z z 1 [k] [k] CP2 [k] [k] [k] DAC [k] 1 β 1 α 1 β 2 α 2 1 x[k] sub−ADC2 sub−ADC1 y[k] CP1
Figure 2.18: A 2nd-order DSM with the proposed calibration scheme.
g1
r1
c1
d1
e1
b1
s1
1
STF
1
NTF
1
CTF
1
[k]
[k]
[k]
[k]
[k]
y[k]
x[k]
AAR
[k]
[k]
Figure 2.19: Calibration signal flow diagram for β1 calibration.
2.4
Second-Order DSM Design Case
Figure 2.18 shows a 2nd-order DSM. It includes two integrators with their transfer functions expressed as H1(z)= α1 1 − β1z−1 H2(z)= α2 1 − β2z−1 (2.29) The internal opamps of the integrators have a dc gain of 8.2 and 7.7 respectively, yielding
α1 = 0.804, β1 = 0.902, α2 = 0.794, and β2 = 0.897. The regular sub-ADC1 following
the 2nd integrator is single comparator. Thus, for this 2nd-order DSM, N = 2 and ∆ = 2. If the integrators are ideal and OSR = 64, the theoretical maximum SQNR is 79 dB for this DSM.
The proposed calibration scheme adjusts β1 and β2 separately. Integrators with
q1[k]×Vc1is injected to the input of the 2nd integrator. A calibration processor, CP1, takes
the sub-ADC1 output y[k] and generates a control signal T1[k] to adjust β1of the 1st
inte-grator. The calibration signal c1[k] is a square wave with fq1frequency, Vc1amplitude, and
50% duty cycle. Calibration processor CP1 is identical to the CP shown in Figure 2.10. In the CP1, its g1[k] signal has a duty ratio of Dg1 and its BPD has a threshold of Nth1.
Its output T1[k] controls the β1of the first integrator such that β1[k]= β0,1+ ∆β1× T1[k].
Figure 2.19 shows the calibration signal flow diagram, where e1[k] is the quantization
noise of sub-ADC1. We have
∆ · Y (z) = STF1(z)X(z)+ NTF1(z)E1(z)+ CTF1C1(z) (2.30) STF1(z)= H1(z)H2(z) 1+ z−1H 2(z)+ z−1H1(z)H2(z) (2.31) NTF1(z) = 1 1+ z−1H 2(z)+ z−1H1(z)H2(z) (2.32) CTF1(z)= H2(z) 1+ z−1H 2(z)+ z−1H1(z)H2(z) (2.33) The sub-ADC1 output y[k] is a summation of the input x[k] shaped by the signal transfer function STF1, the sub-ADC1 quantization e1[k] shaped by the noise transfer function
NTF1, and the calibration signal c1[k] shaped by CTF1. The sub-ADC1 has a conversion
gain of 1/∆. The calibration signal c1[k] go through the CTF1 filter, yielding d1[k].
Thus, embedded in y[k], d1[k] is the step response of CTF1 triggered by c1[k]. This step
response settles toward a final value of
Vcf1 = Vc1×CTF1(1) ≈ Vc1×
1 − β1
α1 (2.34)
The Vcf1 value is used to detect β1. The calibration processor CP1 masks y[k] with g1[k]
to extract only the valid Vcf1information. It then uses the AAR processing to diminish the
calibration fluctuation caused by x[k] and e1[k]. The CP operation is identical to those
described in Section 2.3. Following the design considerations outlined in Section 2.3, we choose fq1 = fs/32, Dg1 = 7/16, Vc1 = 0.1∆, ∆β1 = 0.01, and Nth1 = 96. The resulting
time constant is τ1= 176421.
To calibrate β2, a calibration signal c2[k] = q2[k] × Vc2 is injected to the input of
sub-ADC1. The output of the 1st integrator is digitized by an extra ADC, sub-ADC2, yielding w[k]. For this design case, sub-ADC2 is a single comparator. A calibration
2.4. SECOND-ORDER DSM DESIGN CASE 27
g2
r2
c2
d2
e1
e2
2
CTF2
CTF
b2
s2
2
STF
1
[k]
[k]
[k]
[k]
[k]
x[k]
[k]
w[k]
AAR
[k]
[k]
Figure 2.20: Calibration signal flow diagram for β2 calibration.
processor, CP2, takes w[k] and generates control signal T2[k] to adjust β2 of the 2nd
integrator. Design parameters are the calibration signal frequency fq2, the calibration
signal amplitude Vc2, the g2[k] signal duty ratio Dg2, the BPD threshold Nth2, and the β2
control step size ∆β2. Figure 3.7 shows the calibration signal flow diagram, where e1[k]
is the quantization noise of sub-ADC1 and e2[k] is the quantization noise of sub-ADC2.
We have ∆ · W (z) = E2(z)+ STF2(z)X(z)+ CTF2(z) [E1(z)+ C2(z)] (2.35) STF2(z)= H1(z)+ z−1H1(z)H2(z) 1+ z−1H 2(z)+ z−1H1(z)H2(z) (2.36) CTF2(z)= −z−1H1(z) 1+ z−1H 2(z)+ z−1H1(z)H2(z) (2.37) The sub-ADC2 output w[k] is a summation of the input x[k] shaped by the signal transfer function STF2, the sub-ADC1 quantization e1[k] shaped by CTF2, the sub-ADC2
quan-tization e2[k], and the calibration signal c2[k] shaped by CTF2. The sub-ADC2 has a
conversion gain of 1/∆. The calibration signal c2[k] go through the CTF2filter, yielding
d2[k]. Thus, embedded in w[k], d2[k] is the step response of CTF2 triggered by c2[k].
This step response settles toward a final value of
Vcf2 = Vc2×CTF2(1) ≈ Vc2× −
1 − β2
α2
(2.38) The Vcf2value can be used to detect β2. The CP2 operation is similar to the CP1 operation.
Figure 2.21: Output spectra of the 2nd-order DSM design case.
polarity of g2[k] is inverted. To simplify design, c2[k] is identical to c1[k] and CP2 is
identical to CP1. The design parameters fq2, Dg2, Vc2, ∆β2, and Nth2 are identical those
for c1[k] and CP1.
Figure 2.21 shows the DSM output spectra before and after calibration. The input is a sine wave with a frequency of (41/216)f
s and an amplitude of −3 dBFS. Assuming an
OSR of 64, the resulting SQNR is 52 dB before calibration, and is improved to 72 dB after calibration. Assume the DSM input bandwidth is 2 MHz and the sampling frequency is
fs = 256 MHz, yielding an oversampling ratio OSR = 64. Then a calibration time of
2 × 3τ1 = 4.1 msec is required for both β1 and β2 to converge from 0.9 to 0.995. Besides
this, the SFDR grows from 57.71 dB to 87.25 dB.
The injected calibration signals increase the swing of the internal nodes in the loop filter. As Vcjgrows, j is 1 or 2, not only a rise of the output swing of integrators, but also
a rise of the quantization noise power caused by the overload of the internal quantizer are discovered. Therefore, the amplitude of Vcjis restricted and the bounds are decided from
2.4. SECOND-ORDER DSM DESIGN CASE 29
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Amplitude of V (Full Scale)
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Peak SQNR
c
1is inserted
c
2is inserted
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Amplitude of V (Full Scale)
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Magnitude of integrtor ouput
1st-integrator, c1 is injected.
1st-integrator, c2 is injected. 2nd-integrator, c1 is injected.
2nd-integrator, c2 is injected.
Figure 2.22: The amplitude of Vcj vs. peak SQNR as well as the magnitude of integrator
bj Vc b1 w[k] j+1 b Hj−1 H1 ADCj CP Hj Hj+1 HP ADC1 DAC x[k] T[k] c[k] y[k] = q[k]
Figure 2.23: Calibration of a CIFB DSM.
simulations, such as peak SQNR and the magnitude of integrator output. For the second-order one-bit DSM demonstrated earlier, these two kinds of simulations are plotted in Figure 2.22. Along as Vcjis smaller than 0.4, the decrease of SQNR is no more than 2dB.
If Vcj > 0.4, Vc1especially, a noticeable loss of peak SQNR will happen. As regards the
magnitude of integrator output, the higher amplitude of Vcj is, the lagger magnitude of
integrator output will be.
2.5
High-Order DSM Design Case
The proposed calibration can be applied to DSMs of any structure. Figure 2.23 is a DSM containing P cascaded integrators with distributed feedback (CIFB). The trans-fer functions of the integrators are H1(z), . . . , HP(z). The j-th integrator, where j =
1, · · · , P , is modeled as Hj(z)= αj 1 − βjz−1 or αjz −1 1 − βjz−1 (2.39) The calibration corrects the β of the integrators one at a time. To calibrate the j-th inte-grator, Hj(z), a calibration signal c[k] is injected at the input of the (j+ 1)-th integrator,
while the output of the (j − 1)-th integrator is digitized as w[k] and send to the calibration processor (CP). The CP output T [k] adjusts the β of the j-th integrator.
Figure 2.24 shows the c[k]-to-w[k] signal flow, in which x[k] and the quantization er-rors generated by the sub-ADCs are neglected. The function F (z) is the transfer function
2.5. HIGH-ORDER DSM DESIGN CASE 31 bj bj Hj Hj Hj w[k] c[k] w[k] c[k] y[k] y[k] F G F G
Figure 2.24: c[k]-to-w[k] signal flow in a CIFB DSM.
from y[k] to w[k]. It involves integrators from H1to Hj−1. The function G(z) is the
trans-fer function from c[k] to y[k]. It involves integrators from Hj+1 to HP but without the
contribution from Hj(z). In the bottom half of Figure 2.24, the signal flow is redrawn so
that F (z) and G(z) are in the forward signal path and Hj(z) and bjHj(z) are the feedback
paths. The c[k]-to-w[k] transfer function is CTFj(z) = W(z) C(z) = −F(z)G(z) Hj(z)F (z)G(z)+ bjHj(z)G(z)+ 1 (2.40) The dc gain of CTFj(z) is CTFj(0). Since the signal structure of F (z) is a cascade of
integrators, we have F (0) 1 and CTFj(0) ≈ −F(0)G(0) Hj(0)F (0)G(0) = − 1 Hj(0) = −1 − βj αj (2.41) We design c[k] as a square wave with an amplitude of Vc. In each c[k] cycle, the step
response of CTFj(z) is embedded in w[k]. We design the c[k] period to be long enough
so that the step response can settle toward its final value, which is Vcf,j = Vc×−(1−βj)/αj.
The CP extracts Vcf,j to determine the polarity of 1 − βj, and then adjusts βj to make it
b1 bj w[k] Vc j−1 b bP H1 CP Hj Hj−1 ADCj Hj+1 HP ADC1 T[k] c[k] = q[k] x[k] DAC y[k]
Figure 2.25: Calibration of a CIFF DSM.
To calibrate the 1st integrator, H1(z), the calibration signal c[k] is injected to the
input of the 2nd integrator and the DSM regular digital output y[k] is used as the CP input. The corresponding c[k]-to-y[k] signal flow is similar to those shown in Figure 2.24, but without the −F (z) block and the outer Hj feedback path. The c[k]-to-y[k] transfer
function is CTF1(z)= Y(z) C(z) = G(z) 1+ b1H1(z)G(z) (2.42) Since b1H1(0)G(0) 1, the dc gain of CTF1(z) can be approximated by
CTF1(0) ≈ G(0) b1Hj(0)G(0) = 1 b1Hj(0) = 1 − β1 b1α1 (2.43)
When c[k] is applied, the final value of the CTF1(z) step response is Vcf,1 ≈ +Vc(1 −
β1)/(b1α1). The polarity of Vcf,1is different from that of Vcf,j where j 6= 1.
Figure 2.25 is a DSM containing P cascaded integrators with distributed feedforward summation (CIFF). Similar to the CIFB DSM shown in Figure 2.23, to calibrate the j-th integrator, Hj(z), a calibration signal c[k] is injected at the input of the (j + 1)-th
integrator, while the output of the (j − 1)-th integrator is digitized as w[k] and send to the calibration processor (CP). The CP output T [k] adjusts the β of the j-th integrator. Figure 2.26 shows the c[k]-to-w[k] signal flow, where
F1(z)= H1(z) × H2(z) × · · · × Hj−1(z)
F2(z)= b1H1(z) × b2H2(z) × · · · × bj−1Hj−1(z)
G(z)= bj+1Hj+1(z) × bj+2Hj+2(z) × · · · × bPHP(z)
2.5. HIGH-ORDER DSM DESIGN CASE 33 bj bj Hj 2 F F1 Hj Hj G 2 F F1 c[k] G w[k] y[k] w[k] y[k] c[k]
Figure 2.26: c[k]-to-w[k] signal flow in a CIFF DSM.
From Figure 2.26, it can be shown that CTFj(0) ≈ −1/Hj(0) for j ≥ 2 and CTF1(0) ≈
+1/H1(0).
The proposed calibration technique can correct the β of all integrators in a DSM. It calibrates each individual integrator one at a time. Although a square wave is injected into the DSM for calibration, its effect on the DSM is minuscule. The calibration itself is robust. It can easily converge as long as the amplitude of the square-wave calibration signal c[k] is sufficiently large. It does not require high-precision analog circuitry. It can tolerate the non-linearity of the sub-ADCs. The design procedures for the proposed calibration scheme are similar to those described in Section 2.3 and Section 2.4.
2.5.1
A Third-Order CRFB DSM
Figure 2.27 shows a 3rd-order DSM design case. It employs the cascade of resonators with distributed feedback (CRFB) structure [20]. Its NTF has three zeros, i.e.,
1 c c2 c3 1 z 1 z 1 z 1 z 1 z 1 T 2 w w3 T3 2 T 1 T β 2 α 2 1 1 β1 1 α 1 β3 3 α y[k] [k] [k] [k] CP2 CP3 [k] [k] [k] DAC [k] [k] [k] sub−ADC1 sub−ADC2 sub−ADC3 x[k] CP1 −γ
Figure 2.27: A 3rd-order DSM with the proposed calibration scheme. where ρ= tan−1 s 4β2β3 (β2+ β3− γα2α3)2 −1 ! (2.46) For an ideal case, γ = 0.0064, α1 = 0.145, α2 = 0.474, α3 = 0.789, and all β = 1,
yielding z1 = 1 and z2,3 = e±j2π/128. All zeros are located on the z-plane unit circle. Their
frequencies are 0 and fs/128 respectively. Assume the DSM operates at an oversampling
ratio OSR= 64, and its sub-ADC1 and DAC have N = 3 quantization levels. Then, the DSM can achieve a theoretical maximum SQNR of 90 dB.
From (2.45) and (2.46), if β < 1, then the zeros are moved inside the z-plane unit circle, degrading the NTF’s noise suppression capability in the signal band. Consider a non-ideal case, in which γ = 0.0064, α1 = 0.146, α2 = 0.478, α3 = 0.80, β1 = 0.982,
β2 = 0.940, and β3 = 0.9. This DSM can only achieve a theoretical maximum SQNR of
66 dB with a −5 dBFS input.
As shown in Figure 2.27, the proposed calibration scheme is added to this DSM. The regular sub-ADC and its corresponding DAC have N = 3 quantization levels, yielding ∆= 2/(N − 1) = 1. All calibration signals, c1[k], c2[k], and c3[k], are identical. They
have a frequency fq = fs/64 and an amplitude Vc = 0.1∆. For CP1, Dg1 = 0.125,
Nth1 = 96, and ∆β1 = 0.005, yielding τ1 = 223488. To reduce the analog overhead of
the calibration, sub-ADC2 and sub-ADC3 are realized with a single comparator. For CP2 and CP3, Dg2 = Dg3 = 0.125, Nth2 = Nth3 = 96, and ∆β2 = ∆β3 = 0.005, yielding
![Figure 2.16: β[k] transient response of the 1st-order DSM design case.](https://thumb-ap.123doks.com/thumbv2/9libinfo/8471997.183573/42.893.160.739.184.1072/figure-β-transient-response-order-dsm-design-case.webp)
