The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link standard named by Motorola that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select (chip select) lines. Sometimes SPI is called a “four wire” serial bus, contrasting with three, two, and one wire serial buses.
Figure D - 1: SPI bus with single slave and single master
The SPI bus specifies four logic signals.
1. SCLK (or SCK) --- Serial Clock (output from master).
2. MOSI/SIMO (or SDI or DI or SI) --- Master Output, Slave Input (output from master).
3. MISO/SOMI (or SDO or DO or SO) --- Master Input, Slave Output (output from slave).
4. SS (or CS) --- Slave Select (active low; output from master).
The SPI bus can operate with a single master device and with one or more slave devices. If a single slave device is used, the SS pin may be fixed to logic low if the slave permits it. Some slaves require the falling edge of the slave select to initiate an action. With multiple slave devices, an independent SS signal is required from the master for each slave device. Most devices have tri-state outputs that become high impedance (“disconnected”) when the device is not selected. Devices without tri-state outputs can’t share SPI bus segments with other devices; only one such slave may talk
to the master, and only its chip select may be activated.
To begin a communication, the master first configures the clock, using a frequency less than or equal to the maximum frequency the slave device supports.
Such frequencies are commonly in the range of 1-70 MHz.
The master then pulls the slave select low for the desired chip. If a waiting period is required then the master must wait for at least that period of time fefore starting to issue clock cycles.
During each SPI clock cycle, a full duplex data transmission occurs. The master sends a bit on the MOSI line; the slave reads it from that same line. The slave sends a bit on the MISO line; the master reads it from that same line. Not all transmissions require all four of these operations to be meaningful but they do happen.
Transmissions normally involve two shift registers of some giver word size, such as eight bits, one in the master and one in the slave; they are connected in a ring. Data is usually shifted out with the most significant bit first, while shifting a new least significant bit into the same register. After that register has been shifted out, the master and slave have exchanged register values. Then each device takes that value and does something with it, such as writing it to memory. If there is more data to exchange, the shift registers are loaded with new data and the process repeats.
Transmissions may involve any number of clock cycles. When there are no more data to be transmitted, the master stops toggling its clock. Normally, it then deselects the slave. Transmissions often consist of 8-bit words, and a master can initiate multiple such transmissions if it wishes/needs. However, other word sizes are also common, such as 16-bit words for touchscreen controllers or audio codecs; or 12-bit words for many digital-to-analog or analog-to-digital converters. Every slave on the bus that hasn’t been activated using its slave select line must disregard the input clock and MOSI signals, and must not drive MISO. The master selects only one slave at a
time.
Figure D - 2: A typical hardware setup using two shift registers to form an inter-chip circular buffer
In addition to setting the clock frequency, the master must also configure the clock polarity and phase with respect to the data. Freescale’s SPI Block Guide names these two options as CPOL and CPHA respectively, and most vendors have adopted that convention.
The timing diagram is shown to the below. The timing is further described below and applies to both the master and the slave device.
Figure D - 3: A timing diagram showing clock polarity and phase
• At CPOL = 0 the base value of the clock is zero.
(1) For CPHA = 0, data are read on the clock’s rising edge and data are changed on a falling edge.
(2) For CPHA = 1, data are read on the clock’s falling edge and data are changed on a rising edge.
• At CPOL = 1 the base value of the clock is one (inversion of CPOL = 0).
(1) For CPHA = 0, data are read on clock’s falling edge and data are changed on a rising edge.
(2) For CPHA = 1, data are read on clock’s rising edge and data are changed on a falling edge.
That is, CPHA = 0 means sample on the leading (first) clock edge, while CPHA = 1 means sample on the trailing (second) clock edge, regardless of whether that clock edge is rising or falling. Note that with CPHA = 0, the data must be stable for a half cycle before the first clock cycle. Also, note that no matter what the CPOL and CPHA modes say, the initial clock value must be stable before the chip select line goes active.
This adds more flexibility to the communication channel between the master and slave.
The combinations of polarity and phases are often referred to as modes which are commonly numbered according to the following convention, with CPOL as the high order bit and CPHA as the low order bit:
Mode CPOL CPHA
In the independent slave configuration, there is an independent slave select line for each slave. This is the way SPI is normally used. Since the MISO pins of the slaves are connected together, they are required to be tri-state pins.
Figure D - 5: Typical SPI bus of a master and three independent slaves
There are the advantages of using spi bus:
1. Full duplex communication
2. Higher throughput than I C or SMBus 2
3. Complete protocol flexibility for the bits transferred (1) Not limited to 8-bit words
(2) Arbitrary choice of message size, content, and prupose 4. Extremely simple hardware interfacing
(1) Typically lower power requirements than I C or SMBus due to less circuitry 2 (including pull-ups)
(2) No arbitration or associated failure modes
(3) Slaves use the master’s clock, and don’t need precision oscillators (4) Transceivers are not needed
5. Uses many fewer pins on IC packages, and wires in board layouts or connectors, than parallel interfaces
6. At most one “unique” bus signal per device (chip-select); all others are shared