2.1 Introduction
This chapter lists three sections for designing a high performance of current-steering DAC.
The first is basic resolution requirement or static linearity. In general design, the matching is guaranteed by large size and gate over-drive voltage. The second and the third are code-dependant switching transient (CDST) and code-code-dependant loading variation(CDLV) re-spectively. The static linearity impacts the both signal to noise ratio (SNR) and SFDR.
The effects of CDST and CDLV will result in the degradation of SFDR.
2.2 Static Linearity
The DAC static linearity is specified as differential nonlinearity (DNL) and integral non-linearity (INL). In the design of high-accuracy current steering DACs, the matching prop-erties are the first issue that should be concerned. For example, the DNL and INL of a DAC are shown in Figure 2.1. While the INL is as large as 10LSBs, the spectrum shown in Figure 2.2 is spurious with odd and even order harmonic distortions. As a result, the dynamic performance of a current-steering DAC is limited by not only frequency but also static linearity. This section will discuss the technique for good static linearity.
I. Matching property
In a simple design, we can choose proper device sizes for the matching of transistors
9
Figure 2.1: A DAC with worse DNL and INL
2.2. STATIC LINEARITY 11
Figure 2.2: When the INL is as large as 10LSB in Figure 2.1, the spectrum is spurious with odd and even order harmonic distortions.
Table 2.1: Maximum INL of a 8-bit 5-3 segment DAC INL (max) √
256σ ≤ 0.5LSB DNL(max) √
16σ ≤ 0.5LSB
Table 2.2: The required area versus different gate overdrive
Vov(mV ) 100 150 200 250 300 350
W Lunit (um2)(1σ) 14.1/2 6.4 3.7 2.5 1.8 1.1 W Lunit (um2)(3σ) 127/2 57.6 33.3 22.5 16.2 9.9
[13]. The current mismatch between two transistors can be calculated by matching data and the equation.
σ2∆I
I = 1
W · L ·(4A2V T
Vov + A2β), (2.1)
where σ is the standard deviation of mismatch current, W is the MOSFET width and L is the Length, and AV T and Aβ are the matching parameters from foundry.
For 8-bit with 5-3 segmentation, LSB= 1I, 2I, 4I and MSB = 8I 8I 8I ... Then, the maximum INL and DNL are listed in Table 2.1 and the requirement is less than 0.5 LSB.
Then, the σ and the area are expressed as 1 ×p
256σ ≤ 0.5
σ ≤3.125 × 10−2 2 × (3.125 × 10−2)2× W Lunit ≥4 · 5.812
Vov2 + 0.01622
The required area versus different gate overdrives, Vov, are listed in Table 2.2. Generally, we use three sigma for the yield up to 99.7%, and Table 2.3 is the relation of yield and sigma.
II. Dynamic Element Matching
In the technique of dynamic element matching, the DAC is made of several unit DAC elements which inevitably are subject to random mismatches incurred during IC
fabrica-Table 2.3: The relationship between yield and sigma
σ ×1.0 ×1.4 ×1.6 ×1.8 ×2 ×2.2 ×2.4 ×2.6 ×2.8 ×3.0 yield 68.3 77.0 83.8 89.0 92.8 95.4 97.2 98.4 99.1 99.7
2.2. STATIC LINEARITY 13
Figure 2.3: A 3-bit 3-layer DEM DAC
tion as well as possible systematic circuit and layout mismatches. DAC output signals which usually introduce nonlinear distortion in the overall DAC output signal, often lim-iting the linearity of the overall DAC. In [25, 27, 36, 37, 24], dynamic element matching (DEM) was proposed for high-resolution DACs. They spread the mismatching into noise by selecting unit DAC elements randomly. A 3-bit 3-layer DEM DAC was shown in Fig-ure 2.3, and each layer was controlled by random numbers. The first layer input x[n] is decoded by switch box S3, 1. The x[n] will be randomly distributed into y1[n] to y8[n], so the mismatch of each 1-bit DAC will not be code-dependant. That is, DEM spreads the mismatch into noise floor. In [29, 30], random walk was proposed to reduce the system-atic and graded errors. The random walk is a scheme for the layout placement, and they have good performance on the INL.
III. Calibration and Trimming
Calibration and trimming techniques are the schemes to against the random mismatch, allowing to use small current source transistors. In [17], the authors proposed an fore-ground self-trimming. The off-chin CAL-ADC, shown in Figure 2.4, digitizes the
mis-match of each MSB current cells at star-up step. Then, the mismis-match are stored in memory and a CAL-DAC is used to compensate the total mismatch of the MSB current cells. And in [5], the authors also proposed an off-line self-trimming technique which is based on the trimmable floating gate. The gate can be charged and discharged, and then the current is changed. However, the foreground self-trimming techniques lack of tracking ability of supply and temperature variation. There would be a 0.7 LSB drift over temperature varia-tion form -40 to 85 degrees [20]. As a result, the author proposed background calibravaria-tion technique which can work under the normal operation. The floating current sources [15]
provide the current from the tail node, so the current calibration does not interrupt the normal operation. In [18], the floating source and an analog calibration loop are shown in Figure 2.5. The current comparator locates at right-half side, and the total current of the current source injects into comparator at node A. The cell current and IB are summed to be compared with IR. If IR is larger than the total current, the Cstore will be discharged.
During the guard time between two consecutive calibration phases when MSB cells are switched, the parasitic capacitance at node B may discharge due to the temporary current imbalance. To prevent subsequent charge-sharing from causing glitches, the latter is sam-pled by a common tracking capacitor Chold during the phase before the particular MSB be calibrated. This pre-sampled voltage VHi is then used to hold the voltage on node B through a buffer during the guard time to make the transition seamless.
2.3 Code-Dependant Switching Transients(CDSTs)
At the beginning of this section, we define and introduce what code-dependant switching transient is.
Figure 2.6 shows the operation of a single current cell. The current cell contains a current source Iuand a MOSFET current switch M1-M2. Upon the rising edge of clock CK, the binary input Bj[k] is loaded into the latch. Its two complementary outputs, Vs1 and Vs2, drive the current switch, directing the Iucurrent to either output node Vo1or output node Vo2. Figure 2.6 also shows the transient response of the differential output current Io = Io1 − Io2. The output current Io is a combination of an ideal transient response and switching transients. Switching transients occur only when Bj[k] varies. There are
2.3. CODE-DEPENDANT SWITCHING TRANSIENTS(CDSTS) 15
Figure 2.4: Calibrated DAC architecture proposed by Cong
IR
Figure 2.5: Calibrated DAC architecture proposed by Q. Huang
Io
Io
Io
Vs1 Vs2
Vo1 Vo2
Io1 Io2
Vs1 Vs2
Va Iu Bj
Transient Response
Ideal Transient Response
Switching Transients
[k] t
t t
CK
Latch
M1 M2
CK
Figure 2.6: Code-dependent switching transient (CDST).
2.3. CODE-DEPENDANT SWITCHING TRANSIENTS(CDSTS) 17
several sources for switching transients [31], including switch feedthrough through the current switch, timing skew of CK or cell-delay differences [38], finite rise/fall time of Vs1and Vs2, and voltage fluctuation at the common-source node Va.
The Io switching transients from all current cells are summed up at the DAC Vo port.
Assume the switching transients are invariant and identical among all current cells, and the switching transients at the rising edges of Io are the inverse of the switching transients at the falling edges of Io. Then total switching transients appear at Vo are proportional to Di[k] − Di[k − 1]. These identical switching transients do not cause harmonic distor-tion. However, there are device variations in both the current switch and the latch, and there are different CK timing skew for different current cells. Thus, different current cells exhibit different switching transients. Depending on the Di[k] sequence, the sequence of the switching transient summation becomes a nonlinear term, resulting in harmonic distortions. This is called the code-dependent switching transient (CDST) effect. If the input Di[k] is a single-tone sinewave and its frequency is increased, the CDST effect is intensified due to the increase of |Di[k] − Di[k − 1]|. Thus, the DAC SFDR decreases with increasing input frequency.
To reduce variation in switching transients, the Vs1 and Vs2waveforms must be care-fully designed. Matching among current switches, latches, and CK routes must be consid-ered in the design. Adding a cascode stage to the current switch is also a common practice to reduce feedthrough of Vs1 and Vs2into the outputs.
Control signal feed-through
The control signal of one current cell is decoded from input signal Di; in other words, all controls are a function of input Di. And if the function is ideal, the control signals contribute a signal gain into output without distortion. Unfortunately, the feed through paths are different due to the binary architecture and device mismatch. In most of DACs, the size of switches are changed according to the current weighting, so that the junction capacitors are different. As a result, the signal feed through will contribute to harmonic distortion. We use a 12-bit DAC with 6-6 segmentation to simluate the impact of switch size. Figure 2.7 is the unit cell to run this simulation, and only the switch MOSFETs are with transistor model. The resistors, current source, decoder and switch driver are ideal components. As shown in Figure 2.8 and Figure 2.9, the large switch size DAC is more