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A Dissertation
Submitted to Department of Electronics Engineering
and Institute of Electronics
College of Electrical and Computer Engineering
National Chiao-Tung University
in partial Fulfillment of the Requirements
for the Degree of
Doctor of Philosophy
in
Electronics Engineering
June 2011
Hsin-Chu, Taiwan, Republic of China
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High-Speed Current-Steering Digital-to-Analog
Converters
Student : Wei-Hsin Tseng
Advisor : Jieh-Tsorng Wu
Department of Electronics Engineering
and Institute of Electronics
National Chiao-Tung University
Abstract
In communication systems, most of the information processing is performed in the digital domain, but the signal carrying the information must be transmitted using analog signals. Therefore, the use of digital-to-analog(DA) and analog-to-digital(AD) converters are unavoidable. Data converters are critical for connecting signals to the real world, often limiting the accuracy and speed of the overall system. As a result, wide-band high-dynamic-range converters are in high demand.
This thesis focuses on the Digital-to-Analog Converters (DACs). The current-steering structure has been widely used in high-speed DACs, since in this structure the main speed limitation comes from the output node, and high sampling speed is thus easily achieved. However, the non-ideal switching limits the bandwidth of spurious-free dy-namic range(SFDR). The SFDR decreases rapidly with increasing input frequency. There-fore, Digital Random Return-to-Zero(DRRZ) is proposed for the high sampling rate current-steering DAC to maintain high SFDR at high frequency.
SFDR better than 60 dB for a sinewave input up to 460 MHz, and better than 55 dB up to 800 MHz. The DAC consumes 90 mW of power.
In the design of high-accuracy current-steering DACs, current sources with high match-ing property are required and the penalty is large area. Intrinsic and parasitic capacitor loading also degrade the signal bandwidth. The way to reduce loading is using compact current cells. In this thesis, background calibration is proposed to correct the mismatch current caused by small dimension.
To verify the proposed background calibration algorithm, a 12-bit DAC was fabricated in 90nm CMOS technology and using compact current cells. The area of current sources are 1/400 of the required area which is designed for 12-bit resolution. The chip consumes 128mW. Active area is 1100x750um2. At 1.25GS/s sampling rate, the DAC achieves better SFDR than 70dB up to 500MHz input frequency.
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»ñø;. ºÓ»×¾O0` vContents
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English Abstract iii
* v List of Tables ix List of Figures xi 1 Introduction 1 1.1 Motivation . . . 1 1.2 Organization . . . 6
2 Design Considerations for DACs 9 2.1 Introduction . . . 9
2.2 Static Linearity . . . 9
2.3 Code-Dependant Switching Transients(CDSTs) . . . 14
2.4 Code-dependant Loading Variation (CDLV) . . . 28
2.5 Summary . . . 33
3 A 8-Bit 1.6 GS/s 90 nm CMOS DAC 35 3.1 Introduction . . . 35
3.2 Digital Random Return-to-Zero (DRRZ) . . . 37
3.3 Circuit Descriptions . . . 39 vii
4 A 12-Bit 1.25-GS/s Background Calibrated DAC 55
4.1 Introduction . . . 55
4.2 Design for High Signal Bandwidth . . . 57
4.3 DAC Architecture . . . 60
4.4 Current-Cell Background Calibration . . . 65
4.5 Experimental Results . . . 77
4.6 Summary . . . 90
5 Conclusions and Future Works 93 5.1 Conclusions . . . 93
5.2 Recommendations for Future Investigation . . . 94
Bibliography 95
F 101
Publication List 102
List of Tables
2.1 Maximum INL of a 8-bit 5-3 segment DAC . . . 12
2.2 The required area versus different gate overdrive . . . 12
2.3 The relationship between yield and sigma . . . 12
2.4 Different segmentations for —HD3—=70dB . . . 30
3.1 DAC Performance Summary . . . 51
4.1 Dimensions of MOSFETs in the M-DAC . . . 63
4.2 DAC specifications . . . 89
4.3 Comparison of Published High-Speed DACs. . . 90
List of Figures
1.1 Block diagram of multi channel transmitter for cable modem. . . 2
1.2 Harmonic distortions will interference adjacent channel. . . 3
1.3 Application of DAC in Transmitter chain. . . 3
1.4 The ARZ can be expressed as an equivalent switch at output node. . . 4
1.5 Code-dependent loading variation (CDLV). . . 5
2.1 A DAC with worse DNL and INL . . . 10
2.2 When the INL is as large as 10LSB in Figure 2.1, the spectrum is spurious with odd and even order harmonic distortions. . . 11
2.3 A 3-bit 3-layer DEM DAC . . . 13
2.4 Calibrated DAC architecture proposed by Cong . . . 15
2.5 Calibrated DAC architecture proposed by Q. Huang . . . 15
2.6 Code-dependent switching transient (CDST). . . 16
2.7 Unit current cell with ideal current source, resistor and latch driver. The current switches are thick oxide device. . . 18
2.8 Simulated Spectrum with sample rate 1GS/s switches size W=2.44um L=0.24um and SFDR 52.5dB. . . 19
2.9 Simulated Spectrum with sample rate 1GS/s switches size W=1.44um L=0.24um and SFDR 55.3dB. . . 20
2.10 Simulated Spectrum with sample rate 200MS/s switches size W=2.44um L=0.24um and SFDR 64.7dB. . . 21
2.11 SFDR summary of different switch sizes and sampling rates. . . 22
2.12 3 cells out of 63 with 10ps clk skew. . . 24 xi
weak driving strength of 80ps of rising/falling time and others with 50ps. 26 2.15 The latch’s differential output cross-point dominate the voltage fluctuation
of the internal node. . . 27
2.16 Code-dependent loading variation (CDLV). . . 27
2.17 Zuis the simulated output impedance of one current cell when one switch is off. . . 29
2.18 The frequency response of Zu . . . 29
2.19 The required output impedance versus specified SFDR for 12-bit DAC. The degree of segmentation does not influence the output impedance re-quirement. . . 30
2.20 Output impedance requirement of unit current cell vs. bit number of DAC. The CDLV caused HD2, HD3 must larger than 70dB and RLis 50ohm. . 31
2.21 Output impedance requirement of unit current cell vs. bit number of DAC. The single ended INL caused by CDLV must small than 0.5LSB and RL is 50ohm. . . 32
3.1 A current-steering DAC. . . 36
3.2 Non-return-to-zero (NRZ) output waveform of a current-steering DAC. . 37
3.3 Waveforms of a return-to-zero (RZ) DAC. . . 37
3.4 Switching behavior of a current cell in a digital return-to-zero (DRZ) DAC or a digital random return-to-zero (DRRZ) DAC. . . 38
3.5 DAC block diagram. . . 40
3.6 Current cell schematic. . . 42
3.7 Clock buffer and interface timing between digital and analog . . . 43
3.8 Microphotograph of the DRRZ DAC . . . 44
3.9 Measured differential nonlinearity (DNL) and integral nonlinearity (INL). 45 3.10 Output spectrum of the DAC with NRZ. Sampling rate is 1.6 GS/s, input frequency is 107 MHz. . . 46
3.11 Output spectrum of the DAC with DRRZ. Sampling rate is 1.6 GS/s, input
frequency is 107 MHz. . . 47
3.12 Output spectrum of the DAC with NRZ. Sampling rate is 1.6 GS/s, input frequency is 731 MHz. . . 48
3.13 Output spectrum of the DAC with DRRZ. Sampling rate is 1.6 GS/s, input frequency is 731 MHz. . . 49
3.14 Measured SFDR at different signal frequencies. . . 50
3.15 Dynamic performance comparison of published DACs. . . 52
4.1 A current-steering DAC. . . 56
4.2 Code-dependent switching transient (CDST). . . 58
4.3 Code-dependent loading variation (CDLV). . . 59
4.4 A segmented 12-bit DAC. . . 61
4.5 Pseudo random number generator (PRNG). . . 62
4.6 Schematic of the j-th M-DAC current cell. . . . 64
4.7 Zero-phase current-mismatch modulation . . . 66
4.8 Zero-phase current-mismatch modulation . . . 67
4.9 DAC block diagram. . . 68
4.10 Various waveforms in calibration signal path. . . 69
4.11 The C-DAC and BUS master. . . 70
4.12 The C-DAC and transfer function. . . 71
4.13 Dm-to-Damapping function. . . 72
4.14 Schematic of the calibration analog signal path. . . 73
4.15 Mismatch information loss due to the finite output port bandwidth . . . . 75
4.16 Calibration cycle vs. output port bandwidth . . . 77
4.17 Microphotograph of the DAC. . . 78
4.18 Measured DNL and INL before current-cell calibration. . . 80
4.19 Measured DNL and INL after current-cell calibration. . . 80
4.20 Measured DAC full-scale transient response. . . 81
4.21 Measured DAC output spectrum without calibration and DRRZ. Sampling rate is 1.25 GS/s. Input frequency is 40 MHz. . . 82
4.23 Measured DAC output spectrum after calibration but without DRRZ. Sam-pling rate is 1.25 GS/s. Input frequency is 477 MHz. . . 84 4.24 Measured DAC output spectrum after calibration and with DRRZ.
Sam-pling rate is 1.25 GS/s. Input frequency is 477 MHz. . . 85 4.26 Measured SFDR versus input frequencies . . . 87 4.27 Measured SNDR versus input frequencies. The SNDR of the DAC is
limited by the Signal Analyzer . . . 88 4.28 SFDR performance comparison. . . 89
Chapter 1
Introduction
1.1
Motivation
In communication systems, most of the information processing is performed in the digital domain, but the signal carrying the information must be transmitted using analog signals. Therefore, the use of digital-to-analog(DA) and analog-to-digital(AD) converters are un-avoidable. Data converters are critical for connecting signals to the real world, often limiting the accuracy and speed of the overall system and this work focuses on the DACs. Wide-band high-dynamic-range DACs are in high demand, especially for multicarrier ra-dio applications [1, 2]. A simplified architecture of a cable modem head end transmitter is shown in Figure 1.1. The cable modem system consists of multiple channels, where each channel contains a digital modulator and a DAC. When multiple channels are combined simultaneously, as shown in Figure 1.2, the SFDR of the DAC should meet a minimum SFDR. If the SFDR is worse than the requirement,signals in one channel will be corrupted by spurious components from other channels. Therefore, the major challenge for design-ing DAC of frequency domain applications is to obtain a wide-band SFDR. Moreover, if the DAC can provide a high sampling rate and large SFDR bandwidth, the multiple channel signal can be combined in digital domain. Then, the digital code can be delivered by one DAC. Figure 1.3 [3] shows another example, a signal transmission over radio fre-quency (RF) involves a complex system design. A baseband message, typically digital, is converted to an analog signal through a DAC at the beginning of the transmission system
Modulator Modulator Modulator Channel_1 Channel_2 Channel_N DAC Output
Figure 1.1: Block diagram of multi channel transmitter for cable modem.
and a series of analog processing which filtering the signal suitable for RF transmission. If the DACs are designed with good high frequency SFDR, the requirement of filter can be relaxed [4].
In recent years, many arts have been published on high-speed DAC design [1, 5, 6, 7, 8, 4, 9, 10, 11, 12]. Most of these designs concentrate on obtaining good low-frequency performance, but they do not perform well at higher frequencies. In [9], the spectrum shows that spurs, almost harmonic distortions, can be improved because they are higher than the noise floor. Therefore, the goal of this work is to reduce the harmonic distor-tions at high and low frequency. We should know the key points that cause harmonic distortions. At low frequency, the performance is limited by static linearity, DNL and INL, the nonlinearity source is from mismatch of current cells. To design a DAC, de-signers take care of matching by matching properties of MOSFET [13] or use techniques such as calibration [14, 15, 16, 17, 5, 18, 19, 20, 21, 22, 23], dynamic element matching [24, 25, 26, 27, 28], and random walks [29, 30]. That is, several ways can be used to have a good static linearity.
In [17], the measured DNL and INL are good, but SFDR still drops at high frequen-cies. The reason is that the DACs cause more switching transients. Switching transient is the non-ideal temporary waveform at output node when switching occurs. Each
cur-1.1. MOTIVATION 3
frequency
Output
Ch−1
Ch−3
Spurs
Ch−N
Ch−2
Figure 1.2: Harmonic distortions will interference adjacent channel.
90o LPF AGC LPF AGC Q−DAC LO I−DAC PA RF−Filter
Di Di Di Di Vo Iu j B Di Vo1 RZ Vo2 [1] [2] [3] [4] [k] Decoder [k] CK t RZ Latch CK M
1.1. MOTIVATION 5
rent cell has different switching transients due to clock skew, drivers mismatch, signal feed-through, and internal node fluctuation. In other words, they are cell dependant, also called code-dependant, and will result in harmonic distortions. This is why the prior arts perform well at low frequencies but not well at high frequencies. In [31], analog return-to-zero(ARZ) was proposed to mitigate this effect. As shown in Figure 1.4, ARZ can be expressed as an equivalent switch at output node and controlled by the signal RZ. The RZ signal has a phase delay with clock. When RZ is low, the switch will short the output and force the differential current to zero. If switching transient occurs at this state, they would be hidden by the switch. However, the switch is on the signal path, the turn-on resistor must be small for good linearity. Most of high speed DACs output 16 mA of current. It means that the switch will pass 8mA, the area cost of this switch is very high and induce parasitic capacitor, which is a serious disadvantage for high sampling rate.
In this thesis, we proposed a digital return-to-zero (DRZ). It can be realized by only replacing the latch architecture and digital input sequence. Moreover, random sequence is inserted into the digital return-to-zero. Then, the switch transients are randomized into noise floor, and SFDR will be improved. This new technique is digital random return-to-zero, called DRRZ. A lower resolution, 8-bit, DACs was fabricated in 90nm COMS to verify the DRRZ [32], and the sampling rate is 1.6GS/s.
Iu Vo1 Vo2 L R L R Iu u R Cu Vo1 Vo2 L R RL Vo1 Vo2 L R RL Co1 o1
R Io1 Co2 Io2 Ro2
Figure 1.5: Code-dependent loading variation (CDLV).
Figure 1.5 shows another source of harmonic distortion. Each current cell is modeled as an ideal switch on top of an ideal current source Iu in parallel with a resistor Ru and
The capacitor Curepresents the capacitance associated with the output node of the current
source, including the gate capacitance of the current switch. Both Ru and Cu are
con-nected to either the Vo1node or the Vo2 node, depending on the state of the switch. As a
result, the total loadings for output nodes Vo1 and Vo2 vary with digital input Di[k]. This
code-dependent loading variation (CDLV) effect introduces harmonic distortion in the differential output Vo = Vo1− Vo2. Increasing Ruand reducing Cucan mitigate the CDLV
effect. Adding cascode stage to a current source can increase Ru. In most designs, the
CDLV effect at high frequencies is dominated by Cu. The Cu capacitance is determined
by the device dimensions of the current switch and the current source, while the device di-mensions are governed by the matching requirements. The CDLV effect can be mitigated by adding an additional cascode stage following the current switch in each current cell [33, 7, 34]. The MOSFETs in those cascode stages need to have large transconductances to achieve good high-frequency performance [34, 12].
For this work, instead of adding additional cascode stages, we simply use smaller devices for both the current sources and the current switches to reduce Cu. Smaller devices
lead to larger mismatches. However, due to the use of DRRZ, the matching requirement for the current switches is relaxed. We also propose a new calibration algorithm for the using of smaller current cells which will reduce parasitic capacitor; therefore, the DACs would be operated in higher sampling rate. A 12-bit 1.25GS/s DAC[35] is implemented as a design example.
1.2
Organization
The organization of the thesis is described as follows:
Chapter 2 discusses the highlight to design a high speed high performance current-steering DACs. Including transient effect, finite output impedance effect and static linear-ity. And introduce the techniques to improve the static and dynamic performances.
Chapter 3 describes a 8-bit and with a high sampling rate of 1.6GS/s DAC. This DAC is designed to demonstrate the digital random return-to-zero(DRRZ) can improve the high output frequency SFDR.
1.2. ORGANIZATION 7
technique to overcome the mismatch due to small size. Since small size is used for high speed and wide SFDR bandwidth.
Chapter 2
Design Considerations for DACs
2.1
Introduction
This chapter lists three sections for designing a high performance of current-steering DAC. The first is basic resolution requirement or static linearity. In general design, the matching is guaranteed by large size and gate over-drive voltage. The second and the third are code-dependant switching transient (CDST) and code-code-dependant loading variation(CDLV) re-spectively. The static linearity impacts the both signal to noise ratio (SNR) and SFDR. The effects of CDST and CDLV will result in the degradation of SFDR.
2.2
Static Linearity
The DAC static linearity is specified as differential nonlinearity (DNL) and integral non-linearity (INL). In the design of high-accuracy current steering DACs, the matching prop-erties are the first issue that should be concerned. For example, the DNL and INL of a DAC are shown in Figure 2.1. While the INL is as large as 10LSBs, the spectrum shown in Figure 2.2 is spurious with odd and even order harmonic distortions. As a result, the dynamic performance of a current-steering DAC is limited by not only frequency but also static linearity. This section will discuss the technique for good static linearity.
I. Matching property
In a simple design, we can choose proper device sizes for the matching of transistors 9
2.2. STATIC LINEARITY 11
Figure 2.2: When the INL is as large as 10LSB in Figure 2.1, the spectrum is spurious with odd and even order harmonic distortions.
Table 2.1: Maximum INL of a 8-bit 5-3 segment DAC
INL (max) √256σ ≤ 0.5LSB
DNL(max) √16σ ≤ 0.5LSB
Table 2.2: The required area versus different gate overdrive
Vov(mV ) 100 150 200 250 300 350
W Lunit (um2)(1σ) 14.1/2 6.4 3.7 2.5 1.8 1.1
W Lunit (um2)(3σ) 127/2 57.6 33.3 22.5 16.2 9.9
[13]. The current mismatch between two transistors can be calculated by matching data and the equation.
σ2∆I I = 1 W · L ·( 4A2V T Vov + A2 β), (2.1)
where σ is the standard deviation of mismatch current, W is the MOSFET width and L is the Length, and AV T and Aβ are the matching parameters from foundry.
For 8-bit with 5-3 segmentation, LSB= 1I, 2I, 4I and MSB = 8I 8I 8I ... Then, the maximum INL and DNL are listed in Table 2.1 and the requirement is less than 0.5 LSB. Then, the σ and the area are expressed as
1 ×p256σ ≤ 0.5 σ ≤3.125 × 10−2 2 × (3.125 × 10−2)2× W Lunit ≥4 · 5.812 Vov2 + 0.01622
The required area versus different gate overdrives, Vov, are listed in Table 2.2. Generally,
we use three sigma for the yield up to 99.7%, and Table 2.3 is the relation of yield and sigma.
II. Dynamic Element Matching
In the technique of dynamic element matching, the DAC is made of several unit DAC elements which inevitably are subject to random mismatches incurred during IC
fabrica-Table 2.3: The relationship between yield and sigma
σ ×1.0 ×1.4 ×1.6 ×1.8 ×2 ×2.2 ×2.4 ×2.6 ×2.8 ×3.0
2.2. STATIC LINEARITY 13 S1,2 S1,1 S1,4 S1,3 S2,1 S2,2 S3,1 1−bit DAC 1−bit DAC 1−bit DAC 1−bit DAC 1−bit DAC 1−bit DAC 1−bit DAC 1−bit DAC x[n] 3 1 0 1 1 1 1 1 1 1 1 2 2 2 2 3 3 Layer1 Layer2 Layer3 y[n] b k b k b k b k−1 b k−2 b 0 1 1 1 1 1 1 R[n] y [n] y [n] y [n] y [n] y [n] y [n] y [n] y [n] 1 2 3 4 5 6 7 8
Figure 2.3: A 3-bit 3-layer DEM DAC
tion as well as possible systematic circuit and layout mismatches. DAC output signals which usually introduce nonlinear distortion in the overall DAC output signal, often lim-iting the linearity of the overall DAC. In [25, 27, 36, 37, 24], dynamic element matching (DEM) was proposed for high-resolution DACs. They spread the mismatching into noise by selecting unit DAC elements randomly. A 3-bit 3-layer DEM DAC was shown in Fig-ure 2.3, and each layer was controlled by random numbers. The first layer input x[n] is decoded by switch box S3, 1. The x[n] will be randomly distributed into y1[n] to y8[n],
so the mismatch of each 1-bit DAC will not be code-dependant. That is, DEM spreads the mismatch into noise floor. In [29, 30], random walk was proposed to reduce the system-atic and graded errors. The random walk is a scheme for the layout placement, and they have good performance on the INL.
III. Calibration and Trimming
Calibration and trimming techniques are the schemes to against the random mismatch, allowing to use small current source transistors. In [17], the authors proposed an fore-ground self-trimming. The off-chin CAL-ADC, shown in Figure 2.4, digitizes the
mis-match of each MSB current cells at star-up step. Then, the mismis-match are stored in memory and a CAL-DAC is used to compensate the total mismatch of the MSB current cells. And in [5], the authors also proposed an off-line self-trimming technique which is based on the trimmable floating gate. The gate can be charged and discharged, and then the current is changed. However, the foreground self-trimming techniques lack of tracking ability of supply and temperature variation. There would be a 0.7 LSB drift over temperature varia-tion form -40 to 85 degrees [20]. As a result, the author proposed background calibravaria-tion technique which can work under the normal operation. The floating current sources [15] provide the current from the tail node, so the current calibration does not interrupt the normal operation. In [18], the floating source and an analog calibration loop are shown in Figure 2.5. The current comparator locates at right-half side, and the total current of the current source injects into comparator at node A. The cell current and IB are summed to
be compared with IR. If IR is larger than the total current, the Cstore will be discharged.
During the guard time between two consecutive calibration phases when MSB cells are switched, the parasitic capacitance at node B may discharge due to the temporary current imbalance. To prevent subsequent charge-sharing from causing glitches, the latter is sam-pled by a common tracking capacitor Chold during the phase before the particular MSB be calibrated. This pre-sampled voltage VHi is then used to hold the voltage on node B through a buffer during the guard time to make the transition seamless.
2.3
Code-Dependant Switching Transients(CDSTs)
At the beginning of this section, we define and introduce what code-dependant switching transient is.
Figure 2.6 shows the operation of a single current cell. The current cell contains a current source Iuand a MOSFET current switch M1-M2. Upon the rising edge of clock
CK, the binary input Bj[k] is loaded into the latch. Its two complementary outputs, Vs1
and Vs2, drive the current switch, directing the Iucurrent to either output node Vo1or output
node Vo2. Figure 2.6 also shows the transient response of the differential output current
Io = Io1 − Io2. The output current Io is a combination of an ideal transient response
2.3. CODE-DEPENDANT SWITCHING TRANSIENTS(CDSTS) 15 Bias Gen. Latch Latch 14−Bit DAC 8+2−bit CAL−DAC Calibration Controller CAL−ADC Decoder RAM Din VDD
Figure 2.4: Calibrated DAC architecture proposed by Cong
IR IB Chold Strim Cstore Ssample Spchrg B A VHi VDD VDD
Io Io Io Vs1 Vs2 Vo1 Vo2 Io1 Io2 Vs1 Vs2 Va Iu j B Transient Response
Ideal Transient Response
Switching Transients [k] t t t CK Latch M1 M2 CK
2.3. CODE-DEPENDANT SWITCHING TRANSIENTS(CDSTS) 17
several sources for switching transients [31], including switch feedthrough through the current switch, timing skew of CK or cell-delay differences [38], finite rise/fall time of
Vs1and Vs2, and voltage fluctuation at the common-source node Va.
The Io switching transients from all current cells are summed up at the DAC Vo port.
Assume the switching transients are invariant and identical among all current cells, and the switching transients at the rising edges of Io are the inverse of the switching transients
at the falling edges of Io. Then total switching transients appear at Vo are proportional
to Di[k] − Di[k − 1]. These identical switching transients do not cause harmonic
distor-tion. However, there are device variations in both the current switch and the latch, and there are different CK timing skew for different current cells. Thus, different current cells exhibit different switching transients. Depending on the Di[k] sequence, the sequence
of the switching transient summation becomes a nonlinear term, resulting in harmonic distortions. This is called the code-dependent switching transient (CDST) effect. If the input Di[k] is a single-tone sinewave and its frequency is increased, the CDST effect is
intensified due to the increase of |Di[k] − Di[k − 1]|. Thus, the DAC SFDR decreases
with increasing input frequency.
To reduce variation in switching transients, the Vs1 and Vs2waveforms must be
care-fully designed. Matching among current switches, latches, and CK routes must be consid-ered in the design. Adding a cascode stage to the current switch is also a common practice to reduce feedthrough of Vs1 and Vs2into the outputs.
Control signal feed-through
The control signal of one current cell is decoded from input signal Di; in other words,
all controls are a function of input Di. And if the function is ideal, the control signals
contribute a signal gain into output without distortion. Unfortunately, the feed through paths are different due to the binary architecture and device mismatch. In most of DACs, the size of switches are changed according to the current weighting, so that the junction capacitors are different. As a result, the signal feed through will contribute to harmonic distortion. We use a 12-bit DAC with 6-6 segmentation to simluate the impact of switch size. Figure 2.7 is the unit cell to run this simulation, and only the switch MOSFETs are with transistor model. The resistors, current source, decoder and switch driver are ideal components. As shown in Figure 2.8 and Figure 2.9, the large switch size DAC is more
Vo1
Vo2
Iu : Ideal CS 4uA
R=25ohm
VDD =2.5V
& Latch Driver
Behavior Decoder
VDD
VDD
Figure 2.7: Unit current cell with ideal current source, resistor and latch driver. The current switches are thick oxide device.
2.3. CODE-DEPENDANT SWITCHING TRANSIENTS(CDSTS) 19
Figure 2.8: Simulated Spectrum with sample rate 1GS/s switches size W=2.44um L=0.24um and SFDR 52.5dB.
spurious at sampling rate of 1 GS/s. The SFDRs are 52.5dB and 55.3dB respectively. The feed-through of control signals are passing by the capacitor; therefore, when the sampling clock is down to 200 MS/s, the SFDR shown in Figure 2.10 is higher than 1 GS/s. The simulation results are summarized in Figure 2.11. The SFDR with sample rate 1GS/s of switch size W=1.44um L=0.24um is better than the SFDR of switches size W=2.44um L=0.24um. And the switch size W=2.44um L=0.24um, the SFDR at 200 MS/s of sampling rate is better than at 1 GS/s.
Clock skew between current sources
Figure 2.9: Simulated Spectrum with sample rate 1GS/s switches size W=1.44um L=0.24um and SFDR 55.3dB.
2.3. CODE-DEPENDANT SWITCHING TRANSIENTS(CDSTS) 21
Figure 2.10: Simulated Spectrum with sample rate 200MS/s switches size W=2.44um L=0.24um and SFDR 64.7dB.
2.3. CODE-DEPENDANT SWITCHING TRANSIENTS(CDSTS) 23
matching property if the DAC is designed with calibration. The matching property equa-tion Equaequa-tion (2.2), where σ2∆I
I
is the standard deviation of mismatch current of two cur-rent cells, AV T is the foundry parameter to model the variation of threshold voltage and
A2β is for the size dimension.
σ2∆I I = 1 W · L ·( 4A2V T Vov + A2 β) (2.2)
From the equation, we can know that the increasing 1 bit resolution the area is 4 times larger. That is, the core area of the DAC is growing. Therefore, the imbalance of the clock line becomes serious. The layout of clock line must be tree shaped for timing synchronization. However, buffer in the clock tree may be with variation and wire loading may be different, resulting in clock skew. The clock delay for each current cells are invariant. In other words, the clock skew is cell-dependant, also called code-dependant, and will result in harmonic distortion. We run simulation based on the 12-bit DAC with 6-6 segmentation to examine the impact of clock skew. Assume that, 3 out of the 6-63 equally weighted MSB cells are suffered with clock skew of 10psec. And the DAC current cells are all ideal devices including switches, resistors and current sources. Figure 2.12 shows that the black line is the spectrum of DAC output without clock skew, and the yellow color one is the spectrum of DAC output with clock skew. It’s clearly, that the clock skew induces harmonic distortions. In Figure 2.13, x axis is sampling frequency and y axis is SFDR. The upper line is the SFDR of DAC with lower output frequency. When the sampling clock, Fs, is 250 MHz, the lower output frequency of 0.03Fs is with a 90dBc of SFDR and the higher one of 0.36Fs is 82dBc. Because the clock skew is cell-dependant, the high frequency input will have more switching switches. As the sampling frequency increased, the SFDR of the both line drops dramatically due to the shorter clock period.
Switch driver mismatch
Switch driver mismatch may result in different rising time and falling time or asym-metry rising/falling time [39, 28]. Then, the glitch area or glitch energy becomes cell-dependant. This phenomenon is severe for the high-speed DAC since the glitch area of one sampling period increases with the sampling frequency. Next, we run a simulation by a 12-bit DAC with 6-6 segmentation. The simulation condition is with ideal current sources and behavioral switch drivers. By setting different driving strength of the switch
Figure 2.12: 3 cells out of 63 with 10ps clk skew.
drivers, we can see the spectra shown in Figure 2.14. There is one driver with a weak driving strength of 80ps and others are with driving strength of 50ps. The resulting spec-tra show that the switch driver mismatch also causes harmonic distortion since they are cell-dependant.
Current Switch mismatch
Device mismatch is usually considered in discussions of static linearity [31] men-tioned that device mismatch also contributes to dynamic nonlinearity because switching behavior is dependent on switch transistor parameters such as threshold voltage and ox-ide thickness. These differences of devices introduce code dependencies in the switching transients. The effect of threshold voltage mismatch would be like the current cells with clock skew, and the skews will cause harmonic distortions. Moreover, the current switch mismatch causes different code-dependent settling time constants.
Voltage fluctuation at internal switch node
The internal source coupled node of the current switch should be carefully designed since the fluctuation at the internal node directly impacts the output current. During the
2.3. CODE-DEPENDANT SWITCHING TRANSIENTS(CDSTS) 25
Figure 2.14: Spectra of the DAC’s output signal. 6-6 segmentation only one latch with weak driving strength of 80ps of rising/falling time and others with 50ps.
switching transient, the internal node voltage fluctuation depends on the cross point of control signal [1, 40, 30, 41]. If the MOSFETs of switch pair are all off simultaneously, the current source will enter triode region and a large voltage fluctuation at internal node until one of the switch MOSFET is turn on. As shown in Figure 2.15, in a NMOS current sources of DAC shown in Figure 2.7, the latch’s differential output cross-point dominate the voltage fluctuation of the internal node. This phenomenon will induce both harmonic distortions and noise. Since the amplitude of the voltage fluctuation is direct proportion to switching current cells and the number of switch cells is Di[n] − Di[n − 1], it’s the digital
input filtered by a high pass filter. And this fluctuation becomes serious at high output frequency.
Major carry glitch
The advantage of such binary-weighted DAC is its simplicity and no decoding logic is required, but it’s suffered by large major carry glitch at the mid-code transition [2]. The most significant bit (MSB) current source needs to be matched to the sum of all the other
2.4. CODE-DEPENDANT LOADING VARIATION (CDLV) 27
Cross−A Cross−B Cross−C Cross−D
Internal Node Fluctuation
Latch’s Cross−point
Figure 2.15: The latch’s differential output cross-point dominate the voltage fluctuation of the internal node.
Iu Vo1 Vo2 L R L R Iu u R Cu Vo1 Vo2 L R RL Vo1 Vo2 L R RL Co1 o1
R Io1 Co2 Io2 Ro2
Figure 2.16: Code-dependent loading variation (CDLV).
current sources to within 0.5 LSB’s (least significant bits). That is, the maximum DNL locates at the mid-code transition. The miscode glitch contains highly nonlinear signal components and will manifest itself as spurs in the frequency domain. Thermometer weighted DAC can avoid this major carry glitch, but the cost is unacceptable for high resolution DACs. The DACs are designed with less major carry glitch and lower cost than thermometer weighted by segmentation. The degree of segmentation influence on both the structure of the converter and on its performance.
2.4
Code-dependant Loading Variation (CDLV)
Figure 2.16 shows another source of harmonic distortion. Each current cell is modeled as an ideal switch on top of an ideal current source Iu in parallel with a resistor Ru and
a capacitor Cu. The resistor Ru represents the output resistance of the current source.
The capacitor Cu represents the capacitance associated with the output node of the
cur-rent source, including the gate capacitance of the curcur-rent switch. Both Ru and Cu are
connected to either the Vo1 node or the Vo2 node, depending on the state of the switch.
As a result, the total loadings for output nodes Vo1 and Vo2 vary with digital input Di[k].
This code-dependent loading variation (CDLV) effect introduces harmonic distortion in the differential output Vo = Vo1− Vo2. When Di[k] is a sinewave, the 3rd-order harmonic
distortion caused by the CDLV effect is [42, 43, 34, 12]
HD3= M 4 · RL.d |Zu| 2 (2.3) where M is the total number of current cells, RL,d = 2RL is the differential resistance of
the DAC output loads, and Zuis the output impedance of a single current cell, where
1
Zu
= 1
Ru+ jωCu
. (2.4)
In single-ended application, the CDLV would cause second harmonic distortion
HD2= −20log MRL 4Zu+ 2MRL (2.5) For NMOS DAC shown in Figure 2.17, the Zuin Equation (2.4) is the output impendence
look into the current cell. The simulated results of Zu is drawn in Figure 2.18. The Zo
is dominated by Ruat low frequency, as the frequency is increased then Zuis dominated
by Cu. The slope of Zo versus frequencies in log scale is -1. If the DAC is 12-bit with
6-6 segmentation, there are 63 MSB’s current cells and 6 LSB’s current cells which can be treated as one MSB cell. In other words, M is 64 in Equation (4.1). Assume that
RL.d is 50Ω. The -70 dB HD3 requirement is that Zu must larger than 45 kΩ. Refer to
the Figure 2.18, the Zu is 45 kΩ at output frequency equal to 84 MHz. The -70dB HD3
bandwidth is limited by the large Cu. For the 12-bit, 6-6 segmentation DAC, Figure 2.19
2.4. CODE-DEPENDANT LOADING VARIATION (CDLV) 29
Zo
Figure 2.17: Zu is
the simulated output
impedance of one
current cell when one switch is off.
Figure 2.18: The frequency response of Zu
output impedance requirement is more strict. In Figure 2.21, we also plot the limitation of HD2 and HD3 which are described in Equation (2.5) and Equation (4.1).
The equation describes the maximum single-end INL at middle code [44].
INL= IunitR 2 LM 2 4Rout (2.6) This is the CDLV effect in static performance. If the INL of DAC is specified to 0.5 LSB, the required output impedance can be obtained from the equation Equation (2.6). The re-quired impedance of different resolutions are plotted in Figure 2.21 [42, 43]; nevertheless, the required impedance challenge is not for static linearity since the impedance is easy to be reached.
As shown in Table 2.4, segmentation does not impact the output impedance require-ment. For example, a 12-bit DAC with 7-5 segmentation needs 90 KΩ, and the unit current cell needs 2.88 MΩ. However, 12-bit DAC with 4-8 segmentation has the same impedance requirement for the unit current cell.
Increasing Ru and reducing Cu can mitigate the CDLV effect. Adding cascode stage
Figure 2.19: The required output impedance versus specified SFDR for 12-bit DAC. The degree of segmentation does not influence the output impedance requirement.
Table 2.4: Different segmentations for —HD3—=70dB
Seg. M Rout,MSB IMSB INL DNL λ Vov MSBsize Rout,unit
7-5 128 90KΩ If/128 64σ 8σ λ Vov 32WL 2.88MΩ 6-6 64 45KΩ If/64 64σ 8 √ 2σ λ Vov 64WL 2.88MΩ 5-7 32 22.5KΩ If/32 64σ 16σ λ Vov 128WL 2.88MΩ 4-8 16 11.25KΩ If/16 64σ 16 √ 2σ λ Vov 256WL 2.88MΩ
2.4. CODE-DEPENDANT LOADING VARIATION (CDLV) 31
Figure 2.20: Output impedance requirement of unit current cell vs. bit number of DAC. The CDLV caused HD2, HD3 must larger than 70dB and RLis 50ohm.
Figure 2.21: Output impedance requirement of unit current cell vs. bit number of DAC. The single ended INL caused by CDLV must small than 0.5LSB and RLis 50ohm.
2.5. SUMMARY 33
is dominated by Cu. The Cu capacitance is determined by the device dimensions of the
current switch and the current source, while the device dimensions are governed by the matching requirements.
The CDLV effect can be mitigated by adding an additional cascode stage following the current switch in each current cell [33, 7, 34]. The MOSFETs in those cascode stages need to have large transconductances to achieve good high-frequency performance [34, 12].
2.5
Summary
In this section, we discuss most of the design considerations for high speed current-steering DACs. The key point is to reduce the parasitic loading on the signal path for high signal bandwidth. And carefully chose the size of switch, cross point the switches, layout matching and tree-shape routing for same time constant. Moreover, techniques such as calibration, DEM and return-to-zero can be used but must evaluate the extra penalty.
Chapter 3
A 8-Bit 1.6 GS/s 90 nm CMOS DAC
3.1
Introduction
The current-steering digital-to-analog converts (DACs) can achieve high sampling rate, and thus are commonly used in generating high-frequency signals [6, 1, 7, 10, 34]. Fig-ure 3.1 shows a generic current-steering DAC. It consists of M equally-weighted cur-rent cells. Each curcur-rent cell contains a curcur-rent source of Iu output current, a p-channel
MOSFET pair functioning as a current switch, and a digital latch controlled by a clock CK. The complementary outputs of the latch control the current switch, directing the Iu
current to either the RL load at Vo1 or the one at Vo2. A decoder converts the DAC
dig-ital input Di[k] into M thermometer-code signals Bj[k], where 1 ≤ j ≤ M, such that
Di[k] = P M
j=1Bj[k]. The Bj[k] signal has a binary value of either+1 or −1. Figure 3.2
illustrates the DAC differential non-return-to-zero (NRZ) output waveform Vo = Vo1−Vo2.
The Vo has a voltage range between+MIuRL and −MIuRL, and a step size of 2IuRL.
The DAC static linearity, specified as differential nonlinearity (DNL) and integral non-linearity (INL), is mainly determined by the matching of Iuamong different current cells
and the output resistances of the Iu current sources. There are techniques to improve
the static linearity, which will not be covered in this section. However, even with ideal
Iu current sources, dynamic nonlinearity still occurs. It is manifested as spurious-free
dynamic range (SFDR) degradation shown in the Vo output spectrum when the Di[k]
input is a single-tone sinewave. The SFDR decreases rapidly with increasing input fre-35
L
R
L
R
Vo1
Vo2
j
B
Di
Iu
[k]
[k]
Decoder
CK
Latch
Figure 3.1: A current-steering DAC.
quency. The sources of dynamic nonlinearity are numerous and complex, including code-dependent switching transients [31, 38] and capacitive output impedance of the current cells [42, 34, 43].
The return-to-zero (RZ) technique has been proposed to improve the DAC dynamic performance [31, 15, 18]. The technique adds an output buffer to isolate the output loads from the current switches and executes current switching operation during the zero phase. The DAC dynamic performance can also be improved by modifying the current switching operation to make the switching transients uncorrelated with the input sequence [45, 1, 24].
In this section, we propose a digital random return-to-zero (DRRZ) technique to miti-gate the effect of switching transients on the DAC dynamic performance. A 8-bit 1.6-GS/s current-steering DAC chip was designed to demonstrate the proposed technique.
3.2. DIGITAL RANDOM RETURN-TO-ZERO (DRRZ) 37 Di Di Di Di Vo [1] [2] [3] [4] CK t
Figure 3.2: Non-return-to-zero (NRZ) output waveform of a current-steering DAC.
Vo
Di[1] Di[2] Di[3] Di[4]
CK
t
Z[1] Z[2] Z[3] Z[4]
Figure 3.3: Waveforms of a return-to-zero (RZ) DAC.
3.2
Digital Random Return-to-Zero (DRRZ)
Consider the j-th current cell of the DAC shown in Figure 3.1. Its current switch is driven by Bj[k] ∈ {−1,+1}. When CK changes from low to high, the current switch
may remain unchanged or undergo a (−1)-to-(+1) switching or a (+1)-to-(−1) switching. When the current switch makes a switching, the DAC output Vo experiences a transient
disturbance called switching transient. The (−1)-to-(+1) switching transient and (+1)-to-(−1) switching transient have opposite polarities. For the NRZ DAC, the switching of the current cells is determined by the input Di[k]. Thus, the switching transients are
input-dependent and will result in DAC dynamic distortion.
Di Di Di Di Bj Bj Bj Bj Bj Rj Rj Rj Rj [1] Z[1] [2] Z[2] [3] Z[3] [4] Z[4] 1 1 1 1 1 1 1 1 1 1 1 1 CK [2] [3] [4] [1] [1] [2] [3] [4]
Figure 3.4: Switching behavior of a current cell in a digital return-to-zero (DRZ) DAC or a digital random return-to-zero (DRRZ) DAC.
output [31, 15, 18]. The CK and Vo waveforms of Figure 3.3 show the ARZ operation.
When CK is high, the DAC is in the data phase. It decodes the digital input Di[k], sets up
its internal current switches, and generates an analog output Vo corresponding to Di[k].
When CK is low, the DAC is in the zero phase. The DAC output Vo is forced to zero by
analog switches added at output nodes Vo1 and Vo2. The current switches in the DAC are
switched to reflect the next input Di[k+ 1] during the zero phase. Thus, the switching
transients do not appear in Voto contribute dynamic distortion. The analog switches at the
output nodes must be large enough to eliminate switching transients.
We can generate the RZ Vo waveform without using the analog switches at the output
nodes. As shown in Figure 3.3, when CK is low, the DAC is in a zero phase, Z[k], in which the DAC arranges its internal current switches in such a way that output Vo = 0.
In the Z[k] state, the switch controls, Bj[k], are reset to pre-defined values such that
PM
j=1Bj[k] = 0, assuming M is an even number. However, in this digital
return-to-zero (DRZ) setup, switching transients appear in Vo. Consider the j-th current cell. The
sequence of its switching control, Bj, is shown in Figure 3.4. When CK is high, Bj =
Bj[k] is determined by the input Di[k]. When CK is low, Bj = Rj[k] is a fixed value
of either+1 or −1. In Figure 3.4, Bj[1] = +1 and Bj[2] = +1 have the same value. If
Rj[1]= +1, there will be no switching during the Z[1] period. If Rj[1]= −1, there will
be a (+1)-to-(−1) and a (−1)-to-(+1) transients on both edges of the Z[1] period. Also shown in Figure 3.4, Bj[2]= +1 and Bj[2]= −1 have different values. If Rj[2]= +1, a
(+1)-to-(−1) transient occurs at the right edge of the Z[2] period. If Rj[2]= −1, a
3.3. CIRCUIT DESCRIPTIONS 39
a constant to Rj[k], i.e., Rj[k]= +1 for all k or Rj[k]= −1 for all k. The current switch
transitions are determined by the Bj[k] sequence alone. Their strong correlation with the
input Di[k] yields distortion in Vo. The DRZ in fact introduces more input-dependent
switching transients than the NRZ.
We propose the digital random return-to-zero (DRRZ) technique to randomize the switching transients appearing in DRZ. In this scheme, the switch controls Bj[k] in
the Z[k] phase are dictated by a pseudo random number generator (PRNG), such that PM
j=1Bj[k] = 0. Consider the j-th current cell and the operation sequence shown in
Fig-ure 3.4. When CK is high, Bj = Bj[k] is determined by the input Di[k]. When CK is
low, Bj = Rj[k] becomes a binary random variable which has a value of either+1 or −1.
In Figure 3.4, Bj[1]= +1 and Bj[2] = +1 have the same value. Switch transitions occur
only if Rj[1]= −1. Also shown in Figure 3.4, Bj[2]= +1 and Bj[2]= −1 have different
values. A switch transition occurs at the right edge of the Z[2] period if Rj[2]= +1. On
the other hand, a switch transition occurs at the left edge of the Z[2] period if Rj[2]= −1.
In summary, the DRRZ makes Rj[k] a random sequence, which randomizes the current
switch transitions. When the switching transients are not correlated with the input Di[k],
they appear as noises in Vo and will not cause distortion.
3.3
Circuit Descriptions
Figure 3.5 shows the block diagram of the 8-bit DAC. It is segmented into a 5-bit equally-weighted MSB DAC (M-DAC) and a 3-bit binary-equally-weighted LSB DAC (L-DAC). The M-DAC comprises 31 identical current cells. Each current cell can output an current of 8I, where I is the DAC unit current. The L-DAC comprises 4 current cells which output an current of 1I, 1I, 2I, and 4I respectively. There are two 1I current cells in the L-DAC so that a differential output of zero can be realized. The node Io1and node Io2of all current
cells are tied together respectively to form the two differential DAC output terminals. The two output terminals are connected to two RL resistors to generate the differential Vo as
illustrated in Figure 3.1. When CK is high, the decoder controls both the M-DAC and the L-DAC. The current of the extra 1I current cell in the L-DAC is always directed to the
Di j R j B Io1 Io2 Io1 Io2 32 R Decoder [k] PRNG [k] [k] [k] 31 8 4 32 31 CK MUX Lat 31 MSB Current Celles CK MUX Lat 2I 4I 8I 1I 1I
3.3. CIRCUIT DESCRIPTIONS 41
is an integer from 0 to 255. In our design, I = 80 µA and RL = 25 Ω yield a Vo with a
differential signal range of 1 Vpp.
In this work the devices were sized to fit the 8-bit linearity by matching equation Equation (3.1). σ2∆I I = 1 2 × 1 W · L ·( 4A2V T Vov + A2 β) (3.1)
For 8-bit with 5-3 segmentation, LSB= 1 2 4, MSB = 8 8 8 ...
INL (max) √256σ ≤0.5LSB DNL(max) √16σ ≤0.5LSB 1 ×p256σ ≤ 0.5 σ ≤3.125 × 10−2 2 × (3.125 × 10−2)2× W Lunit ≥4 · 5.812 Vov2 + 0.01622 Vov (mV ) 100 150 200 250 300 350 W Lunit (um2)(1σ) 14.1/2 6.4 3.7 2.5 1.8 1.1 W Lunit (um2)(3σ) 127/2 57.6 33.3 22.5 16.2 9.9 σ ×1.0 ×1.4 ×1.6 ×1.8 ×2 ×2.2 ×2.4 ×2.6 ×2.8 ×3.0 yield 68.3 77.0 83.8 89.0 92.8 95.4 97.2 98.4 99.1 99.7
As shown in Figure 3.5, each current cell contains a multiplexing latch. When CK is high, the latch selects the Bj[k] control from the Di[k] decoder for normal DAC output.
When CK is low, the latch selects the Rj[k] control from a PRNG. The PRNG is a 16-bit
linear feedback shift register. Its 16 outputs and their complements form the 32 Rj[k]
VB1
VB2
Io1
Io2
j
B
j
B
R
j
R
j
CK
[k]
[k]
CK
VDD=1.2V
MUX−Latch
M1
M2
M3
M4
[k]
[k]
M11
M12
M15
M16
M13
M17
M14
M18
VDD=2.5V
Figure 3.6: Current cell schematic.
phase, the entire L-DAC is treated as a single MSB current cell controlled by a single
R32[k] signal.
Figure 3.6 shows the circuit schematic of a current cell. MOSFETs M1 and M2 form a cascode current source. M3 and M4 together function as a current switch. The current source is operated under a 2.5 V supply. M1–M4 are MOSFETs with thick gate oxide. MOSFETs M11–M18 and the two inverters form a level-sensitive MUX-latch. When CK is high, the Bj[k] signal is loaded into the latch. When CK is low, the Rj[k] signal is
loaded into the latch. The MUX-latch is operated under a 1.2 V supply.
As shown in Figure 3.7 sine-wave was translated to fully differential by off-chip trans-former, and a internal differential to single ended amplifier was used before flip-flop which divided the clock by two. With the division function, duty cycle of clock is near to fifty percentages to avoid timing error between digital and analog interface. The digital circuit dealt with data phase signal at rising edge of digital clock and zero phase signal at the falling edge. The analog clock was above 180 degree differ from digital clock; there-fore, level-sensitive MUX-Latch could catch the proper digital signal. For measurement,
3.4. EXPERIMENTAL RESULTS 43 00000000000 00000000000 00000000000 11111111111 11111111111 11111111111 00000000000 00000000000 00000000000 11111111111 11111111111 11111111111 Digital clock : CLKD Analog clock : CLKA F/F Data phase signal Zero phase signal Buffer Buffer CLKD CLKA
Figure 3.7: Clock buffer and interface timing between digital and analog
a direct digital frequency synthesizer (DDFS) was imbedded. All the digital part were implemented by synthesis and auto place and route.
3.4
Experimental Results
The DAC was fabricated in a standard 90 nm CMOS technology. Figure 3.8 shows the chip photograph. The DAC core area is 400×400 µm2. The chip also includes a direct dig-ital frequency synthesizer (DDFS) to generate digdig-ital inputs for DAC testing. Figure 3.9 shows the measured differential nonlinearity (DNL) and integral nonlinearity (INL) of the DAC. The DNL is+0.04/−0.03 LSB and the INL is +0/−0.2 LSB.
Figure 3.10 and Figure 3.11 show the output spectra of the DAC operating at 1.6 GS/s sampling rate, and the input frequency is 107 MHz. For Figure 3.10, the DRRZ function is turned off, and the DAC output waveform is similar to the NRZ Vo waveform shown
in Figure 3.2. For Figure 3.11, the DRRZ function is turned on, and the DAC output waveform is similar to the RZ Vo waveform shown in Figure 3.3. There are no significant
3.4. EXPERIMENTAL RESULTS 45
Figure 3.10: Output spectrum of the DAC with NRZ. Sampling rate is 1.6 GS/s, input frequency is 107 MHz.
3.4. EXPERIMENTAL RESULTS 47
Figure 3.11: Output spectrum of the DAC with DRRZ. Sampling rate is 1.6 GS/s, input frequency is 107 MHz.
Figure 3.12: Output spectrum of the DAC with NRZ. Sampling rate is 1.6 GS/s, input frequency is 731 MHz.
66 dB for the DRRZ DAC. When the input frequency of the DAC is low, the total number of current switches forced to switch is low in each clock cycle. The overall switching tran-sients have little effect on the harmonic distortion of the DAC. Thus, the DRRZ function shows little improvement in SFDR.
Figure 3.12 and Figure 3.13 are DAC output spectra under similar conditions except the input frequency is raised to 731 MHz. When the input frequency of the DAC is high, the total number of current switches forced to switch is high in each clock cycle. The effect of switching transients becomes large and is revealed as the harmonic tones in Figure 3.12. The SFDR is 43 dB and is dominated by the third harmonic. The harmonic
3.4. EXPERIMENTAL RESULTS 49
Figure 3.13: Output spectrum of the DAC with DRRZ. Sampling rate is 1.6 GS/s, input frequency is 731 MHz.
0
200
400
600
800
Output Signal Frequency (MHz)
40
50
60
70
80
SFDR (dB)
DRRZDRZ
NRZ
|20log HD3|Figure 3.14: Measured SFDR at different signal frequencies.
tones are suppressed by the DRRZ operation as illustrated in Figure 3.13. The SFDR is improved to 56.5 dB.
Figure 3.14 shows the measured SFDR of the DAC operated at 1.6 GS/s sampling rate and with different input frequencies. The DAC has three different configurations, which are NRZ, DRZ, and DRRZ. For the NRZ DAC, the measured SFDR is degraded from 65 dB to 42 dB as input frequency increases toward 800 MHz. Employing the DRRZ operation, the DAC can maintain a SFDR larger than 60 dB up to 460 MHz and a SFDR larger than 55 dB up to 800 MHz. Figure 3.14 also shows the measured SFDR of the DRZ DAC. The DRZ setup cannot improve SFDR at all. At low frequencies, the DRZ DAC exhibits a SFDR even worse than the NRZ DAC. This is because, at low frequencies, DRZ introduces more switching transients than NRZ.
3.4. EXPERIMENTAL RESULTS 51
Table 3.1: DAC Performance Summary
Technology CMOS 90 nm Resolution 8 Bits Sampling Rate fs 1.6 GS/s DNL +0.04 / −0.03 LSB INL +0.0 / −0.2 LSB SFDR @fin= 100 MHz 64.5 dB SFDR @fin= 700 MHz 57.0 dB Load Current 20 mA Output Swing 1 Vpp
Supply Voltage (Analog/Digital) 2.5 V / 1.2 V
Power Consumption 90 mW
Core Area 0.16 mm2
output impedance of current cells [42, 34, 43]. It is expressed as
HD3= M 4 · RL,d |Zo| 2 (3.2)
where RL,d = 50 Ω is the differential resistance of the DAC output loads, M = 32 is the
total number of M-DAC current cells, and Zois the output impedance of a M-DAC current
cell. The L-DAC is treated as a single M-DAC current cell. Referring to Figure ??, Zo
is the output impedance looking into the Io1 terminal when M3 is turned on and M4 is
off. The Zo in our design can be modeled as a resistor Ro = 1.9 MΩ in parallel with a
capacitor Co = 10.8 fF. Figure 3.14 indicates that the HD3 of Equation (3.2) is the major
distortion source for the DRRZ DAC with input frequencies higher than 300 MHz. This type of distortion cannot be removed by DRRZ.
The DAC specifications are summarized in Table 4.2. Figure 3.15 compares the dy-namic performance of this DAC against other published DAC works. In order to compare DACs of different sampling rates, the dynamic performance is defined as SFDR × fs,
where SFDR is expressed in power ratio and fs is sampling rate in Hz. Note the reported
DAC is only an 8-bit design. But its dynamic performance is competitive at high signal frequencies.
10
100
1000
Output Signal Frequency (MHz)
10
810
910
1010
11SFDR x f
s[11]
[5]
[1]
[6]
[9]
[8]
[3]
This Work
3.5. SUMMARY 53
3.5
Summary
A CMOS 8-bit 1.6-GS/s current-steering DAC was presented to demonstrate the proposed digital random return-to-zero (DRRZ) technique. The technique requires only a small overhead in digital circuits. The improvement in SFDR of the DAC is 14 dB when the input frequency is 800 MHz.
Chapter 4
A 12-Bit 1.25-GS/s Background
Calibrated DAC
4.1
Introduction
The current-steering digital-to-analog converts (DACs) can achieve high sampling rate, and thus are commonly used in generating high-frequency signals [6, 1, 7, 8, 4, 10, 34, 12]. Figure 4.1 shows a generic current-steering DAC. It consists of M equally-weighted current cells. Each current cell contains a current source of Iuoutput current, a MOSFET
pair functioning as a current switch, and a digital latch controlled by a clock CK. The complementary outputs of the latch control the current switch, directing the Iu current
to either the RL load at Vo1 or the one at Vo2. A decoder converts the DAC digital input
Di[k] into M thermometer-code signals Bj[k], where 1 ≤ j ≤ M. We define the Bj[k]
signal has a binary value of either+1 or −1. Figure 4.1 illustrates the DAC differential non-return-to-zero (NRZ) output waveform Vo = Vo1− Vo2. The Vo has a voltage range
between+MIuRL and −MIuRL, and a step size of 2IuRL.
The DAC static linearity, specified as differential nonlinearity (DNL) and integral non-linearity (INL), is mainly determined by the matching of Iuamong different current cells
and the output resistances of the Iu current sources. Cascode technique is usually used
to increase the output resistance of a current source. The dimension of the transistors in the current sources must be large enough to ensure good Iu matching [13]. There
Vo1 Vo2 L R L R j B Di Iu Di Di Di Di Vo [k] Decoder [k] [1] [2] [3] [4] Latch CK M CK t Figure 4.1: A current-steering DAC.
4.2. DESIGN FOR HIGH SIGNAL BANDWIDTH 57
are techniques that can relax the device matching requirements, including calibrations [14, 15, 17, 18, 20] and dynamic element matching [24].
Besides static linearity, dynamic performance is also crucial for a high-speed DAC. The DAC dynamic performance is manifested as spurious-free dynamic range (SFDR) degradation shown in the output spectrum of Vo when the Di[k] input is a single-tone
sinewave. As for a DAC with poor dynamic performance, its SFDR decreases rapidly with increasing input frequency. The DAC dynamic performance is related to the switching operation of the internal current switches. It induces the code-dependent switch transient (CDST) effect [31, 38, 28] and the code-dependent loading variation (CDLV) effect [42, 34, 43, 12].
This section describes a 12-bit 1.25-GS/s current-steering DAC [35]. We employ the digital random return-to-zero (DRRZ) technique [32] to mitigate the CDST effect and relax matching requirement for current switches. The DRRZ operation also enables a current-cell background calibration. The calibration relaxes the device matching require-ments for the Iucurrent sources, allowing a more compact design of the current cells. The
compact current cell design directly reduces the CDLV effect. The DAC was fabricated using a standard 90 nm CMOS technology. At 1.25 GS/s sampling rate, this DAC chip achieves a SFDR better than 70 dB up to 500 MHz input frequency.
4.2
Design for High Signal Bandwidth
Figure 4.2 shows the operation of a single current cell. The current cell contains a current source Iu and a MOSFET current switch M1-M2. Upon the rising edge of clock CK,
the binary input Bj[k] is loaded into the latch. Its two complementary outputs, Vs1 and
Vs2, drive the current switch, directing the Iu current to either output node Vo1 or output
node Vo2. Figure 4.2 also shows the transient response of the differential output current
Io = Io1− Io2. The output current Io is a combination of an ideal transient response and
switching transients. Switching transients occur only when Bj[k] varies. There are several
sources for switching transients [31], including switch feedthrough through the current switch, timing skew of CK, finite rise/fall time of Vs1 and Vs2, and voltage fluctuation at
Io Io Io Vs1 Vs2 Vo1 Vo2 Io1 Io2 Vs1 Vs2 Va Iu j B Transient Response
Ideal Transient Response
Switching Transients [k] t t t CK Latch M1 M2 CK
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