Chapter 7 Conclusions
A.2 Design of the 4-PAM Symmetric Code
A differential 4-PAM stream has three different transition types, as illustrated in Fig. A.1. Of these three transitions, only type 1 makes a transition to the same magnitude but opposite polarity (symmetric transition). A type 1 transition, generates a zero crossing precisely at the midpoint between two symbols, and is therefore the
Type: 1) Central crossing 2) Misplaced crossing 3) No crossing
Fig. A.1 Three transition types in the differential 4-PAM symbol stream.
most appropriate for clock recovery. Type 2 and type 3 transitions shall be avoided since they convey incorrect phase information [94].
For two adjacent 4-PAM symbols (ex, symbol a and symbol b), we can have the formula
y = [MSB(a)⊕MSB(b)] • [LSB(a)⊕LSB(b)] (A.1)
(⊕ is XOR operation; • is AND operation). If y = 1, it means that this transition is type 1 transition. Therefore, using (A.1), the receiver can detect the type 1 transition and ignore type2 and type3 transition. To improve the jitter on the data transition, a 4-PAM symmetric code is proposed, providing at least one type 1 transition of the differential 4-PAM signal for every ten transmitted symbols. By the 4-PAM symmetric coding scheme, the differential 4-PAM data streams have sufficient density of type1 transitions and only type 1 transitions perform synchronization in the receiver. By do so, it will reduce the jitter by ±25% of the data transition region (Ts) as illustrated in Fig. A.2.
A.2.1 The Structure of 4-PAM Symmetric Code
The 4-PAM symmetric code translates byte-wide data into a 10-bit serial data stream as the 8B/10B transmission code does. The proposed 4-PAM signaling structure adopts parallel inputs of 16-bit data to two 4-PAM symmetric encoders, each of which has 8-bit data input, as depicted in Fig. A.3. The two encoders encode the MSB and LSB part individually, and output 20-bit data from LSB and MSB encoders outputs. The MSB and LSB output bit are combined to generate one symbol with 4-level in amplitude. A data rate of 10 Gbps requires a line rate of 6.25 GBd (one symbol transmitted two bits). Thus, the output of both the MSB encoder and the LSB encoder consists of two 10-bit data words clocked at 625 MHz (equivalent to 10 Gbps in the source data). Therefore, the 4-PAM symmetric code for 4-PAM transmission requires only half the bandwidth required for 2-PAM transmission.
Fig. A.2 Comparisons of type 1 and type 2 transitions in the differential 4-PAM signals.
Fig. A.3 Structure of 4-PAM symmetric encoders and decoders for 4-PAM signaling system.
A.2.2 Low-jitter of Data Transitions
In every cycle (10 symbols), the 4-PAM symmetric code guarantees at least one type 1 transition, which is different from that of the 8B/10B encoder in the differential 4-PAM signal. To obtain the type 1 transition of the differential 4-PAM signal, bit 3 and bit 2 of the 4-PAM symmetric code must always be coded for (1,0) or (0,1), as illustrated in Fig. A.4 (a) with f =g . Combining one MSB bit and one corresponding LSB bit forms one symbol, and then symbol 3 to symbol 2 will be11 / 00 to 00 / 11 or 01 / 10 to 10 / 01. Therefore symbol 3 to symbol 2 produces a type 1 transition and at least one type 1 transition is generated in every 10 symbols.
Furthermore, the third symbol of every 10 symbols occur a type 1 transition and we can obtain the 10-symbols frame synchronization by observing the data stream to find the intervals with highest average density of type1 transitions, as illustrated in Fig.
A.4 (b).
(a)
(b)
Fig. A.4 (a) Type 1 transition in the 4-PAM symmetric code and (b) frame synchronization.
A.2.3 The Design Concept of Running Disparity
DC balancing is achieved by running disparity. The disparity designates the difference between the numbers of 1s and 0s in a defined block of digits, or the instantaneous deviation from the long-term average value of the running digital sum.
The 4-PAM symmetric encoder translates byte-wide data into a 10-bit serial data stream composed of 6-bit and 4-bit sub-blocks. The serial data stream controls the numbers of 1s and 0s in each sub-block transmission to help balance the DC level between the voltage levels denoting 1 and 0. No distinction is made between 6-bit and 4-bit sub-blocks, which are therefore used to compensate each other.
The unit cell concept is used to explain running disparity of the 4-PAM symmetric code. Fig. A.5 plots the disparity (rd) as a function of time or digit intervals (n). For a binary or two-level code (d), each 1s is denoted by a line segment extending over a one-digit interval and rising at a 45º angle, and a 0s is denoted by a falling line. A waveform corresponding to a possible signal during a unit interval is assigned an algebraic value corresponding to its dc component. The 1s and 0s are typically assigned values of +1 and –1, respectively. The formula of disparity is
rd(n) = rd(n-1)+(-1)d+1 (A.2)
The digital sum variation (DSV) is given as the variation in the running disparity sum of the encoded data stream.
Individual 6-bit and 4-bit sub-blocks are complemented in accordance with disparity rules and the difference between the number of 1s and 0s is always 0, ±2 or
±4. The running disparity is positive (+1 or +3) if two or four more 1s than 0s have been transmitted, respectively, and negative (–1 or –3) if two or four more 0s than 1s are transmitted. The running disparity remains unchanged from the previous transmission if the code contains an equal number of 1s and 0s. As illustrated in Fig.
A.6, all sub-block boundaries have running disparity values of ±1 or ±3, which are different from the 8B/10B code boundaries of ±1. The running disparities of ±1 and
±3 make very little difference to the long-term average DC offset. Fig. A.6 clearly demonstrates that the disparity (or DSV) is bounded, and that the run length of the 4-PAM symmetric code is eight, because a fixed type1 transition occurs in the bit 3 and bit 2 positions. The DSV bounded range makes the resultant code DC-balanced,
Fig. A.6 Disparity versus time plot.
i.e. zero spectral power at zero frequency, which is one of the most frequently required code characteristics in transmission via AC-coupled channels.
A.2.4 Error Detection
Like the 8B/10B code design concepts, the error detection in the 4-PAM symmetric code can be implemented in two ways. The first approach checks each packet transmitted for redundancy. Additionally, the first approach validates the transmission of each packet, using a Media Access Control (MAC) layer to identify errors based on the start and end delimiters. A delimiter is a special character which characterizes synchronization. The second approach adopts cyclic redundancy checking (CRC) to identify errors on individual 6-bit or 4-bit code blocks. If the code is a legal 4-PAM symmetric code and does not violate the disparity rules, then no errors arise. In addition to 256 data characters, the 4-PAM symmetric code defines twelve out-of-band indicators which are the same as those of the 8B/10B code and are called special control characters. Special characters are typically used for transmitting link diagnostics and code-words such as ABORT, RESET, SHUTDOWN and IDLE.
A.2.5 Comparison of Transmission Codes
Another novel transmission code 8B5Q that encodes 8 bits into five 4-PAM symbols removing all full-swing transitions to reduces the baud rate and achieves low jitter of timing recovery has been proposed in [95]. For the 4-PAM system, Table A.1 gives the comparison of the 8B/10B code and the 8B5Q code with the 4-PAM symmetric code. The 4-PAM symmetric code has the good characteristics, including DC-balanced, finite run-length, special characters and error detection as the 8B/10B code dose. For the 4-PAM system, the 4-PAM symmetric code can guarantee sufficient type 1 transitions for low-jitter of timing recovery, but the 8B/10B code does not have such property. The 8B5Q code reduces the jitter of timing recovery for 4-PAM system, but does not have good characteristics as the 8B/10B code and the 4-PAM symmetric code do.