Chapter 7 Conclusions
A.3 Architecture and Implementation of 4-PAM Symmetric Encoder / Decoder 157
The overall block diagram of the 4-PAM symmetric encoder architecture is illustrated in Fig. A.7. The straightforward data flow of 4-PAM makes it easy to pipeline to speed up the encoding rate. In this case, the encoder is partitioned into three stages so that it can operate at 13.1 Gbps. A character is encoded in four clock cycles. The 4-PAM symmetric encoder is clocked by a byte rate clock (clk). The Adder block estimates the number of 1s in data_in[7:0], as demonstrated in Fig. A.7.
The Disparity block predicts the next state running disparity state based on the 1s numbers of data_in[7:0].
The MUX_rd block specifies the running disparity from the reset mode signals, int_rd_val[1:0], or the Disparity block output. The control signal k_char denotes whether the data_in[7:0] represents data or control information. For encoding, each incoming byte is split into two sub-blocks. The five binary lines EDCBA (data_in[4:0]) are encoded into the six binary lines abcdei by the abcdei_look_up
TABLE A.1
8B/10B,8B5Q AND 4-PAM SYMMETRIC TRANSMISSION CODES FOR 4-PAM SYSTEM
Frame Synchronization No No Yes
block. Similarly, the three bits HGF (data_in[7:5]) are encoded into the four bits fghj by the fghj_look_up block. The disparity of each sub-block indicates the difference between the numbers of 1s and 0s, where positive and negative disparity numbers represent an excess of 1s and 0s, respectively. The permitted disparity of both abcdei and fghj is 0, ±4 or ±2. Therefore, encoding scheme is DC free by complementing the disparity of each sub-block.
The Special_logic block encodes the eight bits FGHEDCBA (data_in[7:0]) into the ten bits abcdeifghj when FGHEDCBA can not directly be encoded by the abcdei_look_up and fghj_look_up blocks. When the signal k_char is high, the k_code_look_up block generates special characters. Finally, the enc8b_to_10b block integrates the above results and determines the final outputs (rd[1:0], data_out[9:0]).
The overall block diagram of the 4-PAM symmetric decoder architecture is illustrated in Fig. A.8. In this case, the 4-PAM symmetric decoder is pipelined, and therefore a character is decoded in four clock cycles. The 4-PAM symmetric decoder is clocked by a byte rate clock (clk). As demonstrated in Fig. A.8, the Adder block is applied to estimate the number of 1s in data_in[9:0], which is employed by the Disparity block to predict the next state of running disparity. The MUX_rd block determines the running disparity from the reset mode, int_rd_val[1:0] or the Disparity block output. For decoding purposes, each incoming 10-bit data is partitioned into two sub-blocks. The EDCBA_look_up block then decodes the six binary lines abcdei
Fig. A.7 Block diagram of the 4-PAM symmetric encoder.
(data_in[3:0]) are decoded into the three bits HGF by HGF_look_up block. The disparity of each sub-block of the incoming data is the difference between the number of 1s and 0s; positive and negative disparity numbers denote an excess of 1s and 0s, respectively. For both the abcdei and fghj, the permitted disparity is 0, ±2 or ±4. The Special_logic block decodes the ten bits abcdeifghj (data_in[9:0]) into eight bits HGFEDCBA when they can not be directly decoded by the EDCBA_look_up and HGF_look_up blocks. The abcdeifghj value is uniquely decoded according to only the HGFEDCBA value, without any reference to disparity or other parameters. Although many errors may be identified and sent to the error signal by the any_error_look_up block due to the propagation properties of the 4-PAM symmetric code that, even a single-bit error might not be discovered until several characters after the error is introduced. The k_char_logic block determines whether the data_in[9:0] denotes data or control information and generates the k_char signal. If the k_char signal is high, then the data_in contains a special character, and otherwise it contains a data character. Finally, the dec10b_to_8b block integrates the above results and obtains the final outputs (rd[1:0], k_char, data_out[7:0] and error).
A 4-PAM symmetric encoder / decoder were implemented using UMC 0.18 μm standard cell to synthesize the design. The results are summarized in Table A.2.For the source data rate to achieve 10 Gbps, the area of 4-PAM symmetric encoder / decoder are larger than the 8B/10B encoder / decoder by 1,000~1,500 gate count. The area is measured in equivalents of 2-input NAND gates.
Fig. A.8 Block diagram of the 4-PAM symmetric decoder.
Fig. A.9 shows the measurement results of a devised 4-PAM serial link transmitter [96] outputs with all types of transitions (like the 8B/10B for 4-PAM signaling) and data containing only maximum-swing type 1 transition. The measurements are operated at 10 Gbps and Ts is about 0.6 unit interval (UI). These results demonstrate the peak-to-peak jitter of all types of transitions and the jitter of only maximum-swing type1 transitions are about 0.75 and 0.25 Ts. The measurement results are in agreement with our estimation. Therefore, in the receiver, if the 4-PAM symmetric coding scheme with only type 1 transitions is used, then the timing jitter of the data can be decreased by ±25% Ts. When the data or clock jitter decreases, BER will decrease exponentially [85]. For example, assume the standard deviation of clock jitter is 0.02 UI and Ts is about 0.16 UI. In ideal situation, the data jitter of data stream encoded by 4-PAM symmetric code and un-coded data stream are 0 / ±25% Ts.
BER are about 10-15 / 5´10-13 for encoded / un-coded data respectively.
The 4-PAM symmetric code can also be used in 2-PAM system (binary) and preserve all useful characteristics of the 8B/10B code. Fig. A.10 displays the frequency responses of random binary data stream encoded by the 4-PAM symmetric code and the 8B/10B code, and demonstrates that the 4-PAM symmetric code, like the 8B/10B code, has zero spectral power at zero frequency. Therefore, the 4-PAM
TABLE A.2
SYNTHESIS RESULTS OF THE 4-PAM SYMMETRIC ENCODER / DECODER
4-PAM Symmetric
symmetric code is DC-balanced. Although the 4-PAM symmetric code has frame synchronization, the frequency response of the 4-PAM symmetric code does not exhibit any strong tones. The frequency response of the 4-PAM symmetric code is similar to that of the 8B/10B code.
(a)
(b)
Fig. A.9 Measurement results [96] of (a) all types of transitions and (b) only maximum-swing type1 transitions of the differential 4-PAM signal.
A.4 Conclusions
This appendix presents a novel low-jitter transmission code, 4-PAM symmetric code, for 4-PAM signaling in serial links. The proposed method preserves all the good characteristics of 8B/10B code, such as DC-balanced, finite run-length, error detection and special characters. Furthermore, 4-PAM symmetric code guarantees at least one type 1 transition every ten transmitted symbols, and thus can decrease the jitter of transition time by ±25%Ts in 4-PAM system. Using a UMC 0.18μm standard cell, 13.1 Gbps / 11.3 Gbps encoding / decoding can be achieved with about 2506 / 2915 gates.
Fig. A.10 Frequency responses of the 4-PAM symmetric code and the 8B/10B code.
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Vita
Hsiao-Yun Chen was born in Tainan, Taiwan. She received the B.S. degree in electronics engineering from Feng Chia University, Taichung, Taiwan, in 2002 and
Hsiao-Yun Chen was born in Tainan, Taiwan. She received the B.S. degree in electronics engineering from Feng Chia University, Taichung, Taiwan, in 2002 and