Chapter 4
Fig 4.1 shows a 5-GHz Quadrature VCO circuit. It consists of four main parts: a source of negative transconductance (g
m
), an LC-tank circuit, a current source, and output buffers.4-2 QVCO design follow
Fig 4.2 QVCO design follow
(1)Determine the oscillation frequency and satisfied IEEE 802.11a low and middle band. Modulate inductance and capacitance to achieve high Q characteristic of the resonator.
(2)Determine the PMOS and NMOS size and satisfied the lowest noise figure (NF).
(3)Determine the bias circuit and output buffer.
(4)check performance (5)Layout
(6)LPE
(7)re-simulation (8)Tapeout
4-3 QVCO simulation
4-3-1 Resonator simulation
We obtain the higher Q resonator, so we prior the Q of one inductor:
m27 freq=
m27=7.018 x=115.000000
12.00GHz m28 freq=
m28=8.763 x=105.000000
12.00GHz m29 freq=
m29=10.645 x=95.000000
12.00GHz m30 freq=
m30=12.599 x=85.000000
12.00GHz m27 freq=
m27=7.018 x=115.000000
12.00GHz m28 freq=
m28=8.763 x=105.000000
12.00GHz m29 freq=
m29=10.645 x=95.000000
12.00GHz m30 freq=
m30=12.599 x=85.000000
12.00GHz
2 4 6 8 10 12 14 16 18
0 20
10 15
5 18
freq, GHz
Q2
m27 m28 m29 m30
x=rad=65um~115um higher rad, lower inductance
Fig 4.3 Q of the inductor.
In Fig 4.3, rad represents the radius of the inductor. A large radius has a large inductance (radius: m27 > m28 > m29 > m30). A large inductance has a low Q factor.
In order that increase Q of the resonator, we to try increase Q of the inductor best.
C C_Buffer C=0.2224 pF
C C_cross_couple_pair C=0.085 pF
TSMC_CM018RF_NMOS_RF M2
nr=64 w r=8 um lr=0.5 um Type=1.8V triple-w ell TSMC_CM018RF_NMOS_RF
M1
nr=64 w r=8 um lr=0.5 um Type=1.8V triple-w ell
DC_Feed DC_Feed1
V_DC SRC1 Vdc=0.9 V
VAR VAR1 vtune=0.96
EqnVar
DC_Feed DC_Feed3 V_DC SRC3 Vdc=0.9 V TSMC_CM018RF_JUNCAP_W40 D3
nr=jv
V_DC SRC2 Vdc=vtune V
DC_Feed DC_Feed2 TSMC_CM018RF_JUNCAP_W40 D1
nr=jv TSMC_CM018RF_INDS3_SYM L4
lay=6 rad=x um nr=2 w =30 um
TSMC_CM018RF_INDS3_SYM L5
lay=6 rad=x um nr=2 w =30 um
VAR VAR3 jv=18 x=128
Eqn Var
DC_Feed DC_Feed4 V_DC SRC4 Vdc=1.8 V
Term Term1 Z=50 Ohm Num=1
TF TF1 T=1.00
m18 indep(m18)=
m18=2.503E-11 5.145E9 m18 indep(m18)=
m18=2.503E-11 5.145E9
2. 0 E 9 4. 0 E 9 6. 0 E 9 8. 0 E 9 1. 0 E 10 1. 2 E 10 1. 4 E 10 1. 6 E 10 1. 8 E 10
0. 0 2. 0 E 10
-4E-10 -3E-10 -2E-10 -1E-10 0
-5E-10
1E-10 m18
indep(slope)
sl op e
Eqn k2=m18*(19.7192*indep(m18)) indep(k2)
5145000000.000000 k2
2.539599
(a) (b)
Fig 4.4 (a) The resonator of VCO in this work. (b) Q of the resonator.
Before designing the resonator, it is known that oscillation frequency is decided by total inductance of the resonator and total capacitance, in addition, this circuit uses the varactor to reach the specification that the voltage control oscillation frequency, so preserve oscillation frequency in 5.15GHz.
VAR VAR1 vtune=1
Eqn VarVAR VAR3 jv=43 x=128
Eqn VarDC_Feed DC_Feed1
V_DC SRC1 Vdc=0.9 V
DC_Feed DC_Feed3 V_DC SRC3 Vdc=0.9 V TSMC_CM018RF_JUNCAP_W40 D3
nr=jv
V_DC SRC2 Vdc=vtune V
DC_Feed DC_Feed2 TSMC_CM018RF_JUNCAP_W40 D1
nr=jv
TSMC_CM018RF_INDS3_SYM L5
lay=6 rad=x um nr=2 w=30 um TSMC_CM018RF_INDS3_SYM L4
lay=6 rad=x um nr=2 w=30 um Term
Term1 Z=50 Ohm Num=1
TF TF1 T=1.00
m18 indep(m18)=
m18=1.635E-11 5.155E9 m18 indep(m18)=
m18=1.635E-11 5.155E9
2.0E9 4.0E9 6.0E9
0.0 7.0E9
-4E-10 -3E-10 -2E-10 -1E-10 0 1E-10
-5E-10 2E-10
m18
indep(slope)
slo pe
Eqn k2=m18*(19.7192*indep(m18)) indep(k2)
5155000000.000000
k2 1.662296
(a) (b)
Fig 4.5 (a) Traditional resonator structure. (b) Q of the traditional resonator.
Right compared with Fig. 4.5 by Fig. 4.4, in the same inductance value, 2.539 of the
resonant is higher than traditional resonant by 1.662 after improving.
The resonant after improving has three advantages :
[1] Because inductor is not a symmetrical component, symmetry difference of the resonant structure after so relatively Fig. 4.4 is improved for the law of receiving of the traditional resonant cavity of Fig. 4.5 (a), improve resonant after to it constrains to be can restrain harmonic.
[2] Can know in Fig. 4.6, the characteristic with high qualitative factor of resonant originally designed, so relatively high frequency in the adjustable range is taken, the resonant after improving can get a lower phase place .
[3] In the resonant originally designed, two NMOS capacitor contact in series, and connect with the resonant in parallel. NMOS capacitor works in Accumulation region, as the little noise voltage in the varactor and NMOS capacitor [16] [17].
The change of the voltage correctly of NMOS capacitor is contrary to change of the voltage of varactor (as Fig. 4.7 shows). Therefore reduce FM of the noise, in order to reduce the phase noise.
m18 indep(m18)=
m18=2.588E-11 5.255E9 m18 indep(m18)=
m18=2.588E-11 5.255E9
5.0E9 7.0E9
-3E-10 -2E-10 -1E-10 0
-4E-10 1E-10
m18 indep(m18)=
m18=2.709E-11 5.355E9 m18 indep(m18)=
m18=2.709E-11 5.355E9
5.0E9 7.0E9
-3E-10 -2E-10 -1E-10 0
-4E-10 1E-10
m18 indep(m18)=
m18=2.467E-11 5.155E9 m18 indep(m18)=
m18=2.467E-11 5.155E9
5.0E9 7.0E9
-4E-10 -3E-10 -2E-10 -1E-10 0
-5E-10 1E-10
indep(slope)
sl op e
m18
Eqn k2=m18*(19.7192*indep(m18)) indep(k2)
5155000000.000000 k2 2.507286
indep(slope)
sl op e
m18 m18
indep(slope)
sl op e
Eqnk2=m18*(19.7192*indep(m18)) Eqn k2=m18*(19.7192*indep(m18)) indep(k2)
5255000000.000000 k2 indep(k2)
5355000000.000000 k2
2.681412 2.860689
(a) (b) (c)
Fig 4.6 (a)f=5.15GHz (b)f=5.25GHz (c)f=5.35GHz
m34 indep(m34)=
m34=3.608E-13 freq=5.150000GHz
1.800 m35
indep(m35)=
m35=3.016E-13 freq=5.150000GHz
1.800 m34 indep(m34)=
m34=3.608E-13 freq=5.150000GHz
1.800 m35
indep(m35)=
m35=3.016E-13 freq=5.150000GHz
1.800
1.5
1.0 2.0
2.8E-13 3.8E-13
_20050823_ind_C_jv..vtune
_2 005 0823 nd_C_j v. .C y _i
m35
vd
Cy
m34 NMOS capacitor
junction varactor
Fig 4.7 NMOS capacitor and varactor versus vtune.
4-3-2 Complementary cross-coupled oscillator simulation
Because complementary cross-coupled pair offers negative conductance mainly, and noise include flicker noise, shot noise, thermal noise that the initiative component generate. Hence, we are choosing NMOS and PMOS of the cross-coupled pair, will consider according to the size of noise figure of transistor.
And then, noise figure of simulation NMOS and PMOS transistors.
m1 indep(m1)=
m1=7.392 freq=5.250000GHz
19.000 m1 indep(m1)=
m1=7.392 freq=5.250000GHz
19.000
10 20 30 40 50 60
0 70
8 10 12 14 16
6 18
aa15..SP.x
aa 15. .nf (1)
m1
aa25..SP.x
aa 25. .nf (1)
aa35..SP.x
aa 35. .nf (1)
aa45..SP.x
aa 45. .nf (1)
SP.x
nf (1)
aa65..SP.x
aa 65. .nf (1)
aa75..SP.x
aa 75. .nf (1)
aa80..SP.x
aa 80. .nf (1)
NMOS-RF length=0.18um
watch frequency=5.25GHz nf(1) of NMOS-RF V.S
nr=1~64
@wr=1.5um~8um sweep
(a)
m1 indep(m1)=
m1=7.392
freq=5.250000GHz 0.180
m2 indep(m2)=
m2=13.399
freq=5.250000GHz 0.500 m1 indep(m1)=
m1=7.392
freq=5.250000GHz 0.180
m2 indep(m2)=
m2=13.399
freq=5.250000GHz 0.500
0.20 0.25 0.30 0.35 0.40 0.45
0.15 0.50
8 10 12
6
14 m2
NMOS noise figure
@wr=1.5um & nr=19 watch
length:0.18um~0.5um
SP.x
nf (1)
m1
(b)
Fig 4.8 (a)NF versus nr of NMOS; (b)NF versus length of NMOS
In Fig. 4.8 (a ), we can see wr and nr of NMOS transistor, the relation between it and noise figure, then we get, in nr =19 and wr =1.5, there is minimum noise figure. And
then can know that the bigger length is , noise figure is the bigger by Fig. 4.8 (b).
PMOS Length:0.18um sweep:wr=1.5um~5.5um nr=1~64
m2 indep(m2)=
m2=4.397 freq=5.250000GHz
64.000 m4 indep(m4)=
m4=10.698 freq=5.250000GHz
10.000
m6 indep(m6)=
m6=5.963 freq=5.250000GHz
37.000
m1 indep(m1)=
m1=3.546 freq=5.250000GHz
0.500 m3 indep(m3)=
m3=3.546 freq=5.250000GHz
0.500
m5 indep(m5)=
m5=3.546 freq=5.250000GHz
0.500
m7 indep(m7)=
m7=3.546 freq=5.250000GHz
0.500
m2 indep(m2)=
m2=4.397 freq=5.250000GHz
64.000 m4 indep(m4)=
m4=10.698 freq=5.250000GHz
10.000
m6 indep(m6)=
m6=5.963 freq=5.250000GHz
37.000
m1 indep(m1)=
m1=3.546 freq=5.250000GHz
0.500 m3 indep(m3)=
m3=3.546 freq=5.250000GHz
0.500
m5 indep(m5)=
m5=3.546 freq=5.250000GHz
0.500
m7 indep(m7)=
m7=3.546 freq=5.250000GHz
0.500
10 20 30 40 50 60
0 70
5 10 15
0 20
bb15..SP.x
bb1 5. .nf (1) m4
m6 m2
bb25..SP.x
bb2 5. .nf (1)
bb35..SP.x
bb3 5. .nf (1)
bb45..SP.x
bb4 5. .nf (1)
bb55..SP.x
bb5 5. .nf (1)
bb65..SP.x
bb6 5. .nf (1)
bb75..SP.x
bb7 5. .nf (1)
bb80..SP.x
bb8 0. .nf (1)
m1 m3 m5 m7
(a)
m1 indep(m1)=
m1=1.760
freq=5.250000GHz 0.180 m1 indep(m1)=
m1=1.760
freq=5.250000GHz 0.180
0.20 0.25 0.30 0.35 0.40 0.45
0.15 0.50
2.0 2.5 3.0 3.5
1.5 4.0
SP.x
nf (1)
m1
PMOS wr=8um nr=64um
length:0.18um~0.5um
(b)
Fig 4.9 (a)NF versus nr of PMOS; (b)NF versus length of PMOS
In Fig 4.9 can know , width of the same PMOS, width =wr *nr, the wr is smaller, noise figure is the lower. So, the relation determines size of NMOS and PMOS according to this finally.
In decide complementary cross-coupled pair and after adding resonator, because complementary cross-coupled pair has parasitic capacitance, so will increase capacitance of total in resonator, will cause oscillation frequency to drop, while fine tune. Behind is it produce to ask parasitic capacitance of complementary cross-coupled pair again, is it answer to take the place of resonator to fine tune.
4-3-3 PMOS current mirror & output Buffer simulation
785 mV vin 1.02 V VG 1.80 V
1.80 V 1.80 V 1.80 V 1.80 V
0 V vout
0 V 1.51 V VD 1.51 V
VAR VAR2
down_nr=64 down_wr=8 down_lr=0.18
Eqn Var
VAR VAR1
up_nr=64 up_wr=8 up_lr=0.18
Eqn Var
0 A VtSine
SRC2
Phase=0 Damping=0 Delay=0 nsec Freq=5.25 GHz Amplitude=0.666 V Vdc=0.785 V -292 uA 292 uA
-292 uA 292 uA TSMC_CM018RF_PMOS_RF M1
nr=10 wr=1.5 um lr=0.18 um Type=1.8V twin-well
0 A R R1 R=50 Ohm
-8.98 mA 8.98 mA
-8.98 mA 0 A
TSMC_CM018RF_PMOS_RF M3
nr=down_nr wr=down_wr um lr=down_lr um Type=1.8V twin-well
0 A DC_Block DC_Block1 292 uA
-292 uA -292 uA 292 uA
TSMC_CM018RF_NMOS_RF M4
nr=1 wr=1.5 um lr=0.18 um Type=1.8V triple-well
-9.27 mA V_DC
SRC1 Vdc=1.8 V
8.98 mA I_Probe ID3_up
8.98 mA I_Probe ID4_down -8.98 mA 8.98 mA
-8.98 mA 0 A
TSMC_CM018RF_PMOS_RF M2
nr=up_nr wr=up_wr um lr=up_lr um Type=1.8V twin-well
Fig 4.10 Simulation of output buffer
Fig 4.11 Input waveform of output buffer.
Fig 4.12 Output waveform of output buffer.
After swing that the waveform can be intact, we can take the place of it while entering the intact circuit, then fine tune Performance.
4-3-4 Total Performance
x1
vdd2
x1 x2
x1 vbuf f er 1
vbuf f er 2 vdd1
V2 V3
V4 V1
vbuf f er 2 vbuf f er 2
vbuf f er 1 vbuf f er 1
vdd2 vdd1
x2 x2
V4 V3 V1 V2
a vout 1 vout 3
vout 2 vout 4
TSM C_CM 018RF_M I M CAP C16
wt =30 um lt =30 um Type=M I M CAP_SHI ELD
TSM C_CM 018RF_M I M CAP C15
wt =30 um lt =30 um Type=M I M CAP_SHI ELD
TSM C_CM 018RF_M I M CAP C14
wt =30 um lt =30 um Type=M I M CAP_SHI ELD
TSM C_CM 018RF_M I M CAP C13
wt =30 um lt =30 um Type=M I M CAP_SHI ELD
TSM C_CM 018RF_JUNCAP_W40 D4 nr =jv
TSM C_CM 018RF_JUNCAP_W40 D3 nr =jv TSM C_CM 018RF_JUNCAP_W40 D1 nr =jv
TSM C_CM 018RF_JUNCAP_W40 D2 nr =jv TSM C_CM 018RF_M I M CAP
C1 wt =30 um lt =30 um Type=M I M CAP_SHI ELD
TSM C_CM 018RF_M I M CAP C2
wt =30 um lt =30 um Type=M I M CAP_SHI ELD
TSM C_CM 018RF_M I M CAP C3 wt =30 um lt =30 um Type=M I M CAP_SHI ELD
TSM C_CM 018RF_M I M CAP C4
wt =30 um lt =30 um Type=M I M CAP_SHI ELD
TSM C_CM 018RF_M I M CAP C8
wt =30 um lt =30 um Type=M I M CAP_SHI ELD
TSM C_CM 018RF_M I M CAP C7
wt =30 um lt =30 um Type=M I M CAP_SHI ELD
TSM C_CM 018RF_M I M CAP C6
wt =30 um lt =30 um Type=M I M CAP_SHI ELD
TSM C_CM 018RF_M I M CAP C5
wt =30 um lt =30 um Type=M I M CAP_SHI ELD
TSM C_CM 018RF_M I M CAP C12
wt =30 um lt =30 um Type=M I M CAP_SHI ELD
TSM C_CM 018RF_M I M CAP C11 wt =30 um lt =30 um Type=M I M CAP_SHI ELD
TSM C_CM 018RF_M I M CAP C10
wt =30 um lt =30 um Type=M I M CAP_SHI ELD
TSM C_CM 018RF_M I M CAP C9 wt =30 um lt =30 um Type=M I M CAP_SHI ELD TSM C_CM 018RF_M I M CAP C20
wt =30 um lt =30 um Type=M I M CAP_SHI ELD
TSM C_CM 018RF_M I M CAP C19
wt =30 um lt =30 um Type=M I M CAP_SHI ELD
TSM C_CM 018RF_M I M CAP C18
wt =30 um lt =30 um Type=M I M CAP_SHI ELD
TSM C_CM 018RF_M I M CAP C17
wt =30 um lt =30 um Type=M I M CAP_SHI ELD
TSM C_CM 018RF_M I M CAP C21
wt =30 um lt =30 um Type=M I M CAP_SHI ELD
TSM C_CM 018RF_M I M CAP C22
wt =30 um lt =30 um Type=M I M CAP_SHI ELD TSM C_CM 018RF_M I M CAP C23
wt =30 um lt =30 um Type=M I M CAP_SHI ELD
TSM C_CM 018RF_M I M CAP C24
wt =30 um lt =30 um Type=M I M CAP_SHI ELD
O scPor t O sc1
M axLoopG ainSt ep=
FundI ndex=1 St eps=10 Num O ct aves=2 Z=1. 1 O hm V=
VAR VAR4 vt une=1. 81 E q n V a r
V_DC SRC6 Vdc=1. 8 V R R16 R=0. 75 O hm L L10 R=
L=1. 2 nH
R R14 R=0. 75 O hm L L8 R=
L=1. 2 nH V_DC
SRC5 Vdc=1. 8 V
R R15 R=0. 75 O hm
L L9 R=
L=1. 2 nH
V_DC SRC3 Vdc=1. 8 V L
L7 R=
L=1. 2 nH R R13 R=0. 75 O hm
V_DC SRC8 Vdc=1. 8 V R R12 R=0. 75 O hm L L6 R=
L=1. 2 nH C
C28 C=0. 625 pF R R8 R=625 O hm V_DC
SRC4 Vdc=1. 8 V
R R11 R=0. 75 O hm
L L5 R=
L=1. 2 nH
C C30 C=0. 625 pF R R10 R=625 O hm
R R9 R=625 O hm C C29 C=0. 625 pF
C C27 C=0. 625 pF
R R7 R=625 O hm V_DC SRC2 Vdc=vt une V
C C26 C=0. 625 pF
R R6 R=625 O hm R
R5 R=625 O hm C C25 C=0. 625 pF
VAR VAR2 a=102 jv=24 E q n V a r
TSM C_CM 018RF_PM O S_RF M 33
nr =P_nr wr =P_wr um lr =P_lr um Type=1. 8V t win- well
TSM C_CM 018RF_PM O S_RF M 32
nr =P_nr wr =P_wr um lr =P_lr um Type=1. 8V t win- well
V_DC SRC7 Vdc=1. 8 V V_DC
SRC9 Vdc=1. 8 V
VAR VAR3
N_nr =20 N_lr =0. 18 N_wr =1. 5 E q n V a r VAR VAR1
P_wr =8 P_nr =30 P_lr =0. 18 E q n V a r
VAR VAR9
buf down_wr =8 buf down_nr =64 buf down_lr =0. 18 E q n V a r VAR VAR8
buf up_wr =8 buf up_nr =64 buf up_lr =0. 18 E q n V a r
V_DC SRC11 Vdc=1. 8 V
V_DC SRC10 Vdc=vt une V VAR
VAR6
r ef p_wr =1. 5 r ef p_nr =10 r ef p_lr =0. 18 E q n V a r
VAR VAR7
r ef n_wr =1. 5 r ef n_nr =1 r ef n_lr =0. 18 E q n V a r
TSM C_CM 018RF_PM O S_RF M 19
nr =buf down_nr wr =buf down_wr um lr =buf down_lr um Type=1. 8V t win- well DC_Block DC_Block3
TSM C_CM 018RF_PM O S_RF M 20
nr =buf up_nr wr =buf up_wr um lr =buf up_lr um Type=1. 8V t win- well
R R3 R=50 O hm DC_Feed DC_Feed3
TSM C_CM 018RF_PM O S_RF M 23
nr =buf down_nr wr =buf down_wr um lr =buf down_lr um Type=1. 8V t win- well
TSM C_CM 018RF_PM O S_RF M 24
nr =buf up_nr wr =buf up_wr um lr =buf up_lr um Type=1. 8V t win- well DC_Feed DC_Feed4
R R4 R=50 O hm
DC_Block DC_Block4
DC_Feed DC_Feed2
R R2 R=50 O hm TSM C_CM 018RF_PM O S_RF M 18
nr =buf up_nr wr =buf up_wr um lr =buf up_lr um Type=1. 8V t win- well
TSM C_CM 018RF_PM O S_RF M 17
nr =buf down_nr wr =buf down_wr um lr =buf down_lr um Type=1. 8V t win- well DC_Block DC_Block2
TSM C_CM 018RF_PM O S_RF M 16
nr =buf down_nr wr =buf down_wr um lr =buf down_lr um Type=1. 8V t win- well
TSM C_CM 018RF_PM O S_RF M 15
nr =buf up_nr wr =buf up_wr um lr =buf up_lr um Type=1. 8V t win- well DC_Block DC_Block1
R R1 R=50 O hm
DC_Feed DC_Feed1
VAR VAR10 r es_nr =64 r es_wr =8 r es_lr =0. 5 E q n V a r
TSM C_CM 018RF_NM O S_RF M 26
nr =r es_nr wr =r es_wr um lr =r es_lr um Type=1. 8V t r iple- well TSM C_CM 018RF_NM O S_RF M 27
nr =r es_nr wr =r es_wr um lr =r es_lr um Type=1. 8V t r iple- well
TSM C_CM 018RF_NM O S_RF M 6
nr =r es_nr wr =r es_wr um lr =r es_lr um Type=1. 8V t r iple- well TSM C_CM 018RF_NM O S_RF M 5
nr =r es_nr wr =r es_wr um lr =r es_lr um Type=1. 8V t r iple- well
VAR VAR5
I t ail_wr =8 I t ail_nr =64 I t ail_lr =0. 18 E q n V a r TSM C_CM 018RF_PM O S_RF M 1
nr =P_nr wr =P_wr um lr =P_lr um Type=1. 8V t win- well
TSM C_CM 018RF_PM O S_RF M 12
nr =I t ail_nr wr =I t ail_wr um lr =I t ail_lr um Type=1. 8V t win- well
TSM C_CM 018RF_PM O S_RF M 3
nr =P_nr wr =P_wr um lr =P_lr um Type=1. 8V t win- well TSM C_CM 018RF_PM O S_RF M 4
nr =P_nr wr =P_wr um lr =P_lr um Type=1. 8V t win- well
TSM C_CM 018RF_PM O S_RF M 25
nr =I t ail_nr wr =I t ail_wr um lr =I t ail_lr um Type=1. 8V t win- well
TSM C_CM 018RF_I NDS3_SYM L3
lay=6 r ad=a um nr =2 w=30 um TSM C_CM 018RF_I NDS3_SYM
L4
lay=6 r ad=a um nr =2 w=30 um
I _DC SRC12 I dc=1 m A
TSM C_CM 018RF_NM O S_RF M 28
nr =N_nr wr =N_wr um lr =N_lr um Type=1. 8V t r iple- well
TSM C_CM 018RF_NM O S_RF M 29
nr =N_nr wr =N_wr um lr =N_lr um Type=1. 8V t r iple- well TSM C_CM 018RF_NM O S_RF
M 30
nr =N_nr wr =N_wr um lr =N_lr um Type=1. 8V t r iple- well TSM C_CM 018RF_NM O S_RF M 31
nr =N_nr wr =N_wr um lr =N_lr um Type=1. 8V t r iple- well TSM C_CM 018RF_PM O S_RF M 34
nr =P_nr wr =P_wr um lr =P_lr um Type=1. 8V t win- well
TSM C_CM 018RF_PM O S_RF M 35
nr =P_nr wr =P_wr um lr =P_lr um Type=1. 8V t win- well TSM C_CM 018RF_PM O S_RF M 2
nr =P_nr wr =P_wr um lr =P_lr um Type=1. 8V t win- well
TSM C_CM 018RF_NM O S_RF M 8
nr =N_nr wr =N_wr um lr =N_lr um Type=1. 8V t r iple- well
TSM C_CM 018RF_NM O S_RF M 9
nr =N_nr wr =N_wr um lr =N_lr um Type=1. 8V t r iple- well
TSM C_CM 018RF_NM O S_RF M 10
nr =N_nr wr =N_wr um lr =N_lr um Type=1. 8V t r iple- well TSM C_CM 018RF_NM O S_RF M 11
nr =N_nr wr =N_wr um lr =N_lr um Type=1. 8V t r iple- well I _DC SRC1 I dc=1 m A TSM C_CM 018RF_I NDS3_SYM L1
lay=6 r ad=a um nr =2
w=30 um TSM C_CM 018RF_I NDS3_SYM
L2
lay=6 r ad=a um nr =2 w=30 um TSM C_CM 018RF_PM O S_RF
M 13
nr =r ef p_nr wr =r ef p_wr um lr =r ef p_lr um Type=1. 8V t win- well
TSM C_CM 018RF_NM O S_RF M 14
nr =r ef n_nr wr =r ef n_wr um lr =r ef n_lr um Type=1. 8V t r iple- well
Fig 4.13 VCO intact circuit
1. Output power(Single-end)
(a)
(b)
(c)
Fig 4.14 (a)f=5.15GHz (b)f=5.25GHz (c)f=5.35GHz
We can see by Fig 4-14, the fundamental frequency of the resonator after improving has differed by 31dB with second harmonic, and the fundamental frequency of the traditional structure is usually only lack of 20dB with the second harmonic.
Resonator after improve, it is good that the symmetry of the circuit will come than the traditional resonator, it is can suppress more harmonic distortion.
Output power (Differential)
Fig 4.15 In-phase of output.
As us while differential output, define a first I
+
、Q+
、I-
、Q-
. Then differential output = I+
-I-
, as Fig 4-15 shows , it is differential output, the ones that can know the second harmonic is pressed are very low, it is more linear to represent circuit in this designed.Finally, another differential output = Q
+
-Q-
also.2. The output of Time domain waveform
(a)
(b)
(c)
Fig 4.16 (a)f=5.15GHz (b)f=5.25GHz (c)f=5.35GHz
The resonator after improving is avoided to make the restrain amplitude too big, so the sine wave of this structure is difficult to be distorted.
3. Frequency versus vtune
Fig 4.17 Frequency V.S vtune
Because consider to process deviation, it will be bigger in the design of tuning voltage, it is from vtune =0.4V to 3V must stabilize oscillation.
Frequency sweep designed is from 4.913 ~ 5.538GHz, up to the tuning frequency range of 625MHz. In order to reduce Kvco, the possible one has tuning voltage between 1V and 1.8V.
Can know by Fig 4.17, this design the frequency of three centers of IEEE 802.11a and corresponding vtune:
Frequency Tuning voltage(vtune) 5.15GHz 1.07V
5.25GHz 1.39V 5.35GHz 1.81V
4. Phase noise V.S vtune
Fig 4.18 Phase noise versus vtune.
Because our resonator structure is to adopt Crystal-liked structure, characteristic with high qualitative factor and according to Leeson’s formula:
( )
⎪⎭
⎪⎬
⎫
⎪⎩
⎪⎨
⎧
⎟⎟⎠
⎜⎜ ⎞
⎝ + ⎛
⎥⎥
⎦
⎤
⎢⎢
⎣
⎡
⎟⎟⎠
⎜⎜ ⎞
⎝
⎛ +
⎟⎟⎠
⎜⎜ ⎞
⎝
= ⎛
2 2
2 2 1 1
2 log 2
10 ,
m m vco m
c s
m o vco
m f
V K f
f P
FkT Qf
K f f
L
(4-3-1)The resonator of high Q can get a lower phase place. We can be proved in Fig. 4.18.
In addition when vtune is smaller than 0.9V, in relatively low frequency on the adjustable range is taken, because VCO has higher gain, will be by the last Kvco leading factor in the phase noise, in addition, because new resonator of structure of us increase more two NMOS than tradition, so will offer the noise extra, so when vtune is smaller than 0.9V, the phase place of our structure will rise.
5. Pushing figure
Fig 4.19 Pushing figure
V figure MHz
pushing 65
6 . 1 8 . 1
151 . 5 164 .
5 =
−
= −
If pushing figure is great, oscillation frequency is very apt to change with Vdd. Here, we have two solutions:
(1)Consider the Layout: Will add the extra capacitor to and filter noise by the power.
(2)Consider the bias voltage: Put into steady voltage IC (LM317 ) and stabilize the power
6. Pulling figure
(1)VSWR=1~3(Rloasd≦50 ohm)
Fig 4.20 Pulling figure
Acting as VSWR a change to 3, its frequency drops 10MHz.
(1)VSWR=1~3(Rloasd≧50 ohm)
Fig 4.21 Pulling figure
Acting as VSWR a change to 3, its frequency probably rise 5MHz.
Table 1: VCO performance
Parameter Value
Supply voltage(V
dd
) 1.8VCenter frequency(f
c
) 5.25 GHzTuning range 5.15GHz ~ 5.35GHz
Tuning voltage(V
tune
) 1.07V~1.81VVCO sensitivity(K
vco
) 270.27 MHz/VVCO bias current 18.5mA
Buffer amp. Bias current 34.32mA
Power consumption without buffer(Vdd=1.8V) 33.3mW Power consumption with buffer(Vdd=1.8V) 95.07mW
Phase Noise @1MHz offset from fc -107.948dBc/Hz
Here, phase noise of though the output buffer is -107.948 dBc/Hz, phase noise of not added buffer is up to -118.085 dBc/Hz; And using the buffer amount examined. Just combine in WLAN, supply with Mixer and Frequency synthesizer use, can get higher phase place , let the efficiency of the whole system be increased.
Table 2: VCO performance comparing with other authors.
School NCTU NCKU
This work
Author Mr. Zheng Mr. Lee
Yu-Cheng Wang
Center Freq 5.3925GHz 5.2GHz
5.25GHz
Supply voltage 2.5V 2.5V
1.8V
Frequency range 5.26~5.525GHz 4.8~5.7GHz
4.913~5.538GHz
Phase noise-102.83dBc/Hz@1
MHz
-106.6dBc/Hz@1
MHz
-107.948dBc/Hz@
1MHz
Output power -22.17dBm@5.43GHz
-11dBm
-6dBm
Power consumption
Without buffer 43.75mW 38.25mW
33.3mW
With buffer 80.75mW
95.07mW
Architecture RC-CR Network RC-CR Network
RC-CR Network
Tech & Year CMOS 0.25μm2002
CMOS 0.25μm 2003
CMOS 0.18μm
2005
4-4 QVCO Layout
1. Layout dispose
Before beginning Layout yet, I will make intact dispose to consider first. We confirm it have Pad for several piece and how much piece wire bonder.
(a)
(b)
Fig 4.22 Pad and wire bonder dispose.
Total pad and wire bonder:
Output signal (V
out1
、Vout2
、Vout3
&Vout4
)：4 Voltage source of buffer(Vbuffer1
&Vbuffer2
)：2 Voltage source of cross couple pair(Vdd1
&Vdd2
)：2 Tuning voltage(Vt)：1Voltage source of NMOS capacitor(Vnmos)：1
Add one GND finally, put the surplus area on Ground Pad finally, in order to reduce parasitic inductance and resistance.
Consider to noise of power supply, will hope to add by-pass capacitor in all input of DC bias voltage. Beside four RF out , should all add by-pass capacitor between DC and Ground. Then we will simulation again, will see whether performance of the circuit changes to some extent.
Fig 4.23 Layout dispose
(1) It is very important that the line of Layout is wide. Have one experience rule , line of 1um wide to is it flow current of 1mA to able to bear. Lead to the fact at most that it is usually on the current sources of output stage and core circuit to be able to bear the design not flowing.
(2) In order to prevent too many parasitic capacitance from producing, there are places to cross in all metal, try one's best to separate thickness of oxide layer of a layer. Oxidize one layer of thickness averagly and invite 1.66um.
(3) In order to prevent the effect of Pad from being too big, so metal and device all try one's best to have safe distance of 30um with Pad.