中 華 大 學

中 華 大 學

碩 士 論 文

應用於 IEEE 802.11a WLAN 四相位壓控振 盪器之設計

IEEE 802.11a WLAN CMOS Quadrature Voltage-Controlled Oscillator

系 所 別：電機工程學系碩士班 學號姓名：M09201021 王昱椉 指導教授：田慶誠 博士

中華民國 九十四 年 十二 月

應用於 IEEE 802.11a WLAN 四相位壓控振盪器之設計 IEEE 802.11a WLAN CMOS Quadrate

Voltage-Controlled Oscillator

研究生：王昱椉 指導教授：田慶誠 博士 中華大學電機工程學系碩士班

中文摘要

在通信以及訊號處理系統中，振盪器扮演著重要的角色。振盪器是微波收發器 前端電路中提供本地振盪源訊號(LO signal)的關鍵元件。收發前端需要振盪訊號來 進行調變或解調的工作。因此振盪器的信號品質直接地影響整個系統的表現。一般 來說，常將訊號分成 I/Q 兩通道，增加其適用的頻寬，為了減低雜訊的影響，設計 時大多採用差動型式。因此，收發電路中常需使用四相位正交訊號輸出的振盪器，

才可進行調變或解調。低相位雜訊且發射電路中常需使用四相位正交訊號輸出的振 盪器，才可進行調變或解調。低相位雜訊且寬頻的振盪器一直是設計者所追求的目 標。

本論文中所設計之四相位壓控振盪器電路以國家晶片中心(CIC)提供之台灣積 體電路(TSMC)0.18um製程製作，而此四相位壓控振盪器將以IEEE 802.11a WLAN標準 為規格，設計應用在無線區域網路WLAN上之電路，最後並將之積體電路化。本設計 使用改良後的共振腔(Crystal-liked structure)來達到低相位雜訊的規格，操作電 壓為 1.8V，可調頻率範圍在 5.15～5.35GHz，相位雜訊為-107.948dBc/Hz@1MHz，功 率消耗為 33.3mW，晶片面積為 1.31224 X 1.279 mm

²

。

IEEE 802.11a WLAN CMOS Quadrate Voltage-Controlled Oscillator

Student：Yu-Cheng Wang Advisor：Dr. Ching-Cheng Tien

Institute of Electrical Engineering Chung Hua University

Abstract

In communication and signal process system, the oscillator is playing an important role.

Transceivers often need to quadrature phase oscillator that the signal is being outputted, can modulation or demodulation. The low phase noise and wide-band oscillator have been designer's goals pursued all the time.

This thesis design quadrature phase of voltage-controlled oscillator circuit make with CIC in TSMC 0.18um that offer, and this quadrature phase voltage-controlled oscillator will regard IEEE 802.11a WLAN standard as the specification, will design and apply to the circuit on WLAN, combine its integrated circuit finally.

This design the specification of using the resonance (Crystal-liked structure ) after improving to reach the low phase noise, supply voltage as 1.8V, the adjustable frequency range is in 5.15 ~ 5.35 GHz, the phase noise is -107.948 dBc/Hz@1MHz, power consumption is 33.3mW, the area of the chip is 1.31224 X 1.279 mm

²

.

Acknowledgement

I would like to express the deepest gratitude to my advisor, Professor Ching-Cheng Tien, for his enthusiastic guidance and great patience during my student career.

Thanks are also to everyone in our laboratory who bring me the laughter, joy and encouragement.

Finally, I would like to given my deepest appreciation to my dear parents and to Leticia Yang for their endless love, encouragement, and patience in my life.

Contents

CHINESE ABSTRACT Ⅰ ENGLISH ABSTRACT Ⅱ ACKNOWLEDGEMENT Ⅲ CONTENTS Ⅴ LIST OF FIGURES AND TABLES Ⅵ

Chapter 1 Introduction………..…………..…1

1-1 Motivation………..………..…1

1-2 IEEE 802.11a Standards……….…..…1

1-3 Receiver Architecture………...……….….…..…3

1-4 Organization of the thesis……….4

Chapter 2 Theory of Oscillator Design……….……….….5

2-1 Introduction………..………5

2-2 Oscillation Considerations……….………..…5

2-2-1 Circuit Oscillator Model……….……….….7

2-2-2 Microwave Circuit Model……….………...9

2-2-3 Negative conductance of the Cross-couple pair….……….10

2-3 Quadrature VCO architecture……….………...11

2-3-1 Resonator………..………....14

2-3-2 Complementary cross-coupled oscillator simulation.………...18

2-4 PMOS current mirror & output Buffer simulation………..………....19

2-4-1 Bias of the Complementary cross-coupled pair.………...22

Chapter 3 Phase Noise Analysis………..………...22

3-1 Introduction………..………...22

3-2 Phase Noise Owerview………..………...22

3-3 Phase Noise in VCOs………..………...25

3-4 Quadrature generations………..………...27

Chapter 4 Design of the QVCO………..………...29

4-1 Introduction………..………...29

4-2 QVCO design follow………..………...30

4-3 QVCO simulation………..………...31

4-3-1 Resonator simulation………..…………...31

4-3-2 Complementary cross-coupled oscillator simulation..…………...34

4-3-3 PMOS current mirror & output Buffer simulation..…………...37

4-3-4 Total Performance………..………...38

4-4 QVCO Layout………..………...………...48

4-5 QVCO Measurement………..………...………...53 References

List of Figures and Tables

Fig 1.1 OFDM PHY frequency channel plan for the United States………..….2

Fig 1.2 Receiver architecture………...3

Fig 2.1 Feedback system………...5

Fig 2.2 (a)Feedback system; (b)the signal flow graph………..…7

Fig 2.3 The schematic diagram for one-port negative-resistance oscillators………....8

Fig 2.4 (a)NMOS-only cross-coupled pair; (b)Fig 2.4 (a)’s π-model………...9

Fig 2.5 Quadrature voltage-controlled oscillator schematic……….……...11

Fig 2.6 (a)The parallel resonator; (b)The series resonator………..12

Fig 2.7 (a)Crystal equivalent circuit; (b)Crystal-liked resonator……….……...12

Fig 2.8 Complementary cross-coupled oscillator without resonator………...……15

Fig 2.9 QVCO symmetric………..….15

Fig 2.10 Cross connect of the QVCO………...…...16

Fig 2.11 Classic RC poly-phase filter, shown in two different ways………..17

Fig 2.12 PMOS 的 current mirror and output buffer schematic………...…18

Fig 2.13 Bias of the Complementary cross-couple pair………..19

Fig 3.1 “Perfectly efficient” RLC oscillator……….……...22

Fig 3.2 Phase noise: Leeson versus (3-2-8.)………..……..….…...24

Fig 3.3 Quadrature-coupled LC VCO. (a)Circuit topology; (b)Block diagram…..……....27

Fig 4.1 Quadrature voltage-controlled oscillator schematic……….………..…29

Fig 4.2 QVCO design follow……….……….30

Fig 4.3 Q of the inductor……….31

Fig 4.4 (a) The resonator of VCO in this work. (b) Q of the resonator……….…………..32

Fig 4.5 (a) Traditional resonator structure. (b) Q of the traditional resonator…………....32

Fig 4.6 (a)f=5.15GHz (b)f=5.25GHz (c)f=5.35GHz………..…….33

Fig 4.7 NMOS capacitor and varactor versus vtune………...34

Fig 4.8 (a)NF versus nr of NMOS; (b)NF versus length of NMOS…….………..……...35

Fig 4.9 (a)NF versus nr of PMOS; (b)NF versus length of PMOS……….…………36

Fig 4.10 Simulation of output buffer……….…………..37

Fig 4.11 Input waveform of output buffer………...38

Fig 4.12 Output waveform of output buffer………38

Fig 4.13 VCO intact circuit……….………....39

Fig 4.14 (a)f=5.15GHz (b)f=5.25GHz (c)f=5.35GHz……….………40

Fig 4.15 In-phase of output……….41

Fig 4.16 (a)f=5.15GHz (b)f=5.25GHz (c)f=5.35GHz……….………....42

Fig 4.17 Frequency V.S vtune………...43

Fig 4.18 Phase noise versus vtune……….……….….…44

Fig 4.19 Pushing figure………..….45

Fig 4.20 Pulling figure……….………....46

Fig 4.21 Pulling figure……….……….…...46

Fig 4.22 Pad and wire bonder dispose……….……49

Fig 4.23 Layout dispose………..50

Fig 4.24 Layout of QVCO……….………..…..…..52

Fig 4.25 PCB dispose of QVCO………..…….…..54

Fig 4.26 PCB layout of QVCO………..……...…..55

Fig 4.27 Measure output power and phase noise use spectrum analyzer………..…..56

Fig 4.28 Measure output waveform and phase use oscilloscope………..…..56

Fig 4.29 Measure phase delay produced of the PCB test board and SMA connector…...57

Fig 4.30 Measure phase delay produced of the RG400 cables………..…...57

Fig 4.31 Measure phase of the oscilloscope……….………..…...58

Table 1: VCO performance………...…47

Table 2: VCO performance comparing with other authors………...……..48

Chapter 1 Introduction

1-1 Motivation

The development of single-chip CMOS solutions for the 5-GHz 802.11a wireless local area network (WLAN) standard is desirable to enable implementations at low cost. The full integration of transceivers implies the use of low intermediate frequency (IF) or zero-IF architectures that require quadrature local oscillator (LO) signals for image rejection and demodulation.

Fully integrated voltage-controlled oscillator (VCO) has been one of the focal points of CMOS RF design activities in recent years. Many challengeous design features are high phase accuracy, gain matching, low power dissipation, large tuning range, and low phase noise. There are several options for on-chip quadrature signal generation based on LC resonator. In the first approach, the output of the VCO is applied to a polyphase filter. The second option is the combination of a VCO operating at twice the frequency of interest and a divide-by-two circuit. The third option is to couple two identical oscillators in such a way that forces their outputs to oscillate 90

⁰

out of phase.

1-2 IEEE 802.11a Standards

The OFDM PHY shall operate in the 5 GHz band, as allocated by a regulatory body in its operational region. Spectrum allocation in the 5 GHz band is subject to authorities responsible for geographic-specific regulatory domains (e.g., global, regional, and national). The particular channelization to be used for this standard is

dependent on such allocation, as well as the associated regulations for use of the allocations. These regulations are subject to revision, or may be superseded. In the United States, The FCC is the agency responsible for the allocation of the 5 GHz U-NII bands.

In some regulatory domains, several frequency bands may be available for OFDM PHY-based wireless LANs. These bands may be contiguous or not, and different regulatory limits may be applicable. A compliant OFDM PHY shall support at least one frequency band in at least one regulatory domain. The support of specific regulatory domains, and bands within the domains, shall be indicated by PLME attributes dot11 RegDomainsSupported and dot11 FrequencyBandsSupported [1].

Fig 1.1 OFDM PHY frequency channel plan for the United States

Fig 1.1 shows the canalization scheme for this standard, which shall be used with the FCC U-NII frequency allocation. The lower and middle U-NII sub-bands accommodate eight channels in a total bandwidth of 200MHz. The upper U-NII band accommodates four channels in a 100MHz bandwidth. The centers of the outermost

channels shall be at a distance of 30 MHz from the band’s edges for the lower and middle U-NII bands, and 20 MHz for the upper U-NII band [2].

The OFDM PHY shall operate in the 5 GHz band, as allocated by a regulatory body in its operational region.

1-3 Receiver Architecture

Traditionally, RF receivers employed heterodyne architectures, using discrete filters for image rejection and channel selection. However, as the demand for higher integration increases, the direct conversion architecture has gained popularity due to its simplicity and ease of integration. In this scheme, the RF signal is directly converted to baseband. Consequently, no image reject filter is required after the first amplification stage, and therefore the LNA does not need to drive off-chip high quality filters.

VCO

MIXER MIXER

I ADC

Load

IF=

600-800MHz

Transformer

Q ADC

Load

IF=

600-800MHz

Transformer

passive balun RF

signal

Fig 1.2 Receiver architecture.

Figure 1.2 shows the complete architecture of the receiver presented in this paper, with the differential low noise amplifier (LNA) connected to a set of I/Q mixers which are driven by a voltage-controlled oscillator (VCO) with quadrature outputs.

The of the I/Q mixers can subsequently be connected to another downconversion stage to translate the IF signal to baseband, and thus implementing a Weaver image reject architecture. Another alternative is to directly process the IF signal, after being converted to single-ended by a transformer, using a high-speed ADC followed by a digital signal processor, as suggested in Fig 1.2. The outputs of the mixers are capacitive coupled to the following stages in order to mitigate the effect of DC offset, resulting from LO leakage and signal feed through [3].

1-4 Organization of the thesis

This thesis is organized as follows. Chapter 2 introduces architecture and theory of oscillator design. Chapter 3 is phase noise analysis. Chapter 4 describes the theory, principle, considerations and simulation results of QVCO design. Chapter 5 is conclusion and future prospect.

Chapter 2 Theory of Oscillator Design

2-1 Introduction

Oscillators are an integral part of many electronic systems. Applications range from clock generation in microprocessors to carrier synthesis in cellular telephones, requiring vastly different oscillator topologies and performance parameters. A simple oscillator produces a periodic output, usually in the form of voltage. As such, the circuit has no input while sustaining the output indefinitely.

2-2 Oscillation Considerations 2-2-1 Circuit Oscillator Model

Consider the unity-gain positive feedback circuit shown in Fig. 2.1, from Fig 2.1, we can write

A β A x

x

i o

= −

1

(2-2-1)

Fig 2.1 Feedback system

In summary, if a positive-feedback circuit has a loop gain that satisfies two

conditions:

≥ 1 β

A

(2-2-2)

o

A = 0 o or 360

∠ β

(2-2-3) then the circuit may oscillate at ω

o [4]. The condition (2-2-2) is known as the gain

condition, and (2-2-3) as the frequency of oscillation condition. The frequency of oscillation condition gives the frequency at which the phase shift around the closed loop is 0

⁰

or a multiple of 360

⁰

. In order to ensure oscillation in the presence of temperature and process variations, we typically choose the loop gain to be at least twice or three times the required value.

From the circuit theory we know that oscillation occurs when a network has a pair of complex conjugate poles on the imaginary axis. If the closed-loop gain in (2-2-1) has a pair of complex conjugate poles in the right-half plan, close to the imaginary axis, then, due to the ever-present noise voltage generated by thermal vibrations in the network (which can be represented by a superposition of input noise signals x

s

), a growing sinusoidal output voltage appears. The characteristics of the sinusoidal signal are determined by the complex-conjugate poles in the right-half plan. As the amplitude of the noise-induced oscillation in creases, the amplitude-limiting capabilities of the amplifier produce a change in location of the poles. In the case of a transistor amplifier, as the amplitude of oscillation increases, its value of g

m

decreases from its small-signal values. The changes are such that the complex-conjugate poles move toward the imaginary axis, and at some value of the oscillation amplitude the poles reach the imaginary axis. At this point, (2-2-2) and (2-2-3) are satisfied and the oscillation stabilizes at a constant amplitude values [5].

The stability of a circuit can be determined using he Nyquist stability test. In the Nyquist test, the complex function Aβ is plotted versus frequency and the number of

clockwise encirclements of the point Aβ=1 determines the difference in the number of right-half plan zeroes and poles of the function 1- Aβ.

2-2-2 Microwave Circuit Model

Fig 2.2 (a)Feedback system; (b)the signal flow graph

For a microwave circuit, a closed-loop gain function of the type in (2-2-1) can developed as follows:

Consider the circuit shown in Fig. 2.2(a) and its flow graph in Fig 2.2(b). The coefficient Γ

L

represents the load reflection coefficient and Γ

in

the input reflection coefficient of and active device.

L L

L a

b = Γ

(2-2-4) And

0 0

Z Z

Z Z a

b

L L L

L

L +

= −

=

Γ

(2-2-5)

in in

in a

b = Γ

into (2-2-5)

0 0

Z Z

Z Z a

b

in in in

in

L +

= −

=

Γ

(2-2-6)

And

in

L b

a =

_and

b _L = a _in

(2-2-7) We can express (2-2-7) in the form

1

0 0 0

0 = ⋅ = ⋅ =

+

⋅ − +

= − Γ

⋅ Γ

L L L L in in L L in

in L

L in

L b

a a b a b a b Z Z

Z Z Z Z

Z

Z

(2-2-8)

The Nyquist test can be applied to analyze the function

1 − Γ _L ⋅ Γ _in

determining the

encirclements of the point

Γ _L ⋅ Γ _in = 1

.

A general schematic diagram for one-port negative-resistance oscillators is shown in Fig. 2.3.

Fig 2.3 The schematic diagram for one-port negative-resistance oscillators.

The negative-resistance device is represented by the amplitude and frequency-dependent impedance

We can express (2-2-8) in the form

( )( )

( )( ) _{0 0 0} ^{2 1}

2 0 0 0

0 0

0

0 =

+ +

+

+

−

= − +

+

−

−

Z Z Z Z Z Z Z

Z Z Z Z Z Z Z Z

Z Z Z

Z Z Z Z

in L

in L

in L

in L in

L

in

L

(2-2-9)

And (2-2-9) can be written as

2 0 0 0

2 0 0

0 Z Z Z Z Z Z Z Z Z Z

Z Z Z

Z _{L in} − _L − _in + = _{L in} + _L + _in +

(2-2-10)

Simply

( ) ⁰

2 ₀ + ₀ =

− Z _L Z Z _in Z

(2-2-11)

= 0 + _in

L Z

Z

(2-2-12) Equation (2-2-12) is shown

( ) 0

Re Z _L + Z _in =

(2-2-13)

^Im ( Z _L ⁺ Z _in ) ^{= 0}

(2-2-14) Since the load is passive (Z

L

> 0), equation (2-2-13) indicates that Z

in

< 0. The equation (2-2-13) governs the energy conservation whereas (2-2-14) dominates the frequency of the oscillation. A negative resistance indicates an energy source and a positive resistance means an energy sink [6].

2-2-3 Negative conductance of the Cross-couple pair

Fig 2.4 (a)NMOS-only cross-coupled pair; (b)Fig 2.4 (a)’s π-model

In Fig. 2.4(a) is the NMOS-only cross-coupled pair schematic. The signal phase shift from gate end V1 of M2 to drain end V2 is 180

⁰

. The extra phase shift from the feedback loop between gate to drain of M1 is also 180

⁰

. Thus, the loop results in positive feedback. From another viewpoint, NMOS-only cross-coupled pair can generate negative conductance. In Fig. 2.4(b), we can calculate the input impedance:

From Kirchhoff’s voltage law, we know

I i

i _{D 1} = _{D 2} ≡

(2-2-15)

=

−

=

g V g V

i _{D 1 m 1 gs 1 m 1}

(2-2-16)

−

+

=

−

=

g V g V

i _{D 2 m 2 gs 2 m 2}

(2-2-17) Then

I V I V I

V Z _in V

− +

−

+

− = −

≡ (2-2-18) Substituting (2-2-15) and (2-2-16) and (2-2-17) into (2-2-18) gives

2 1 2

1 1 1

1 1

m m m

m

in I g g

g I

Z g − = − −

−

=

(2-2-19)

When

g _{m 1}

=

g _{m 2}

=

g _m

, we obtain

m

in g

Z

=− 2 (2-2-20) When the negative conductance is larger than conductance of resonator is satisfied, the circuit will oscillates. The NMOS-only and the Complementary cross-coupled oscillator should be biased in saturation region to obtain the larger transconductance

[6] [7].

2-3 Quadrature VCO architecture

Fig 2.5 Quadrature voltage-controlled oscillator schematic

As shown in Fig 2.5, this architecture is consisted of following three part: resonator、

complementary cross-coupled oscillator、current mirror and output buffer。

2-3-1 Resonator

There are two types of traditional resonator ：series resonator, parallel resonator, as

shown in Fig 2.6

Fig 2.6 (a)The parallel resonator; (b)The series resonator.

The oscillation frequency of the resonators in Fig 2.6 (a) and Fig 2.6 (b) is as follows respectively.

1 1

1

C

o

=

L

ω

or

2 2

1

C

o

=

L

ω

(2-3-1) The meaning of Equation (2-3-1) is, as the oscillation frequency of shaking has determined, we can form the oscillation frequency that we want with inductance and capacitance [8].

This thesis adopts Crystal-liked structure (see Fig 2.7 (b))

Fig 2.7 (a)Crystal equivalent circuit; (b)Crystal-liked resonator.

According to Leeson’s formula [9],

{ }

⎪

⎭

⎪⎬

⎫

⎪⎩

⎪⎨

⎧

⎟⎟

⎟⎟

⎠

⎞

⎜⎜

⎜⎜

⎝

⎛ Δ Δ

⎥ +

⎥

⎦

⎤

⎢⎢

⎣

⎡

⎟⎟⎠

⎜⎜ ⎞

⎝

⎛ + Δ

=

Δ

ω

ω ω

ω ω ³

2 1

2 1 2 1

log

10

^{o f}

sig Q

P

L FkT

(2-3-2)

where

L{Δω} phase noise in dBc/Hz;

ω

o

angle frequency of oscillation in Hz;

Δω angle frequency offset from the carrier in Hz;

F noise figure of the transistor amplifier;

k Boltzmann’s constant in J/K;

T temperature in K;

P

sig

RF power produced by the oscillator in W;

3

1 f

ω

Δ flicker noise corner frequency in Hz;

Q unloaded tank Q;

It is important to note that the factor F is an empirical fitting parameter and therefore must be determined from measurements, diminishing the predictive power of the phase-noise equation. Furthermore, the model asserts that

3

1 f

ω

Δ , the boundary

between the

( )

Δ

ω

¹

²

and 1

₃ ω

Δ regions, is precisely equal to the 1/f corner of device noise. However, measurements frequently show no such equality, and thus one must generally treat

3

1 f

ω

Δ as an empirical fitting parameter as well. Also, it is not

clear what the corner frequency will be in the presence of more than one noise source with 1/f noise contribution. The frequency at which the noise flattens out is not always equal to half the resonator bandwidth,

Q

o

2

ω

.

Both the ideal oscillator model and the Leeson model suggest that increasing

resonator Q and signal amplitude are ways to reduce phase noise. The Leeson model additionally introduces the factor F, but without knowing precisely what it depends on, it is difficult to identify specific ways to reduce it. The same problem exists with

3

1 f

ω

Δ as well. Blind application of these models has periodically led to earnest but

misguided attempts to use active circuits to boost Q. Sadly, increase in Q through such means are necessarily accompanied by increases in F as well, preventing the anticipated improvements in phase noise. Again, the lack of analytical expressions for F can obscure this conclusion, and one continues to encounter various doomed oscillator designs based on the notion of active Q boosting.

According to equation (2-3-2)，there are three methods to reduce phase noise:

(1)Choose low noise figure (F) transistors (2)Increase signal power of the oscillator output (3)Choose higher Q resonator

Method one will be explained in section 2-3-2 in details.

Method two will be explained in section 2-3-3 in details.

Method three, because our resonator uses a crystal-liked structure which has a high Q characteristic, it can produces lower phase noise.

In chapter 4, we will demonstrate that the crystal-liked resonator has a high Q characteristic.

2-3-2 Complementary cross-coupled oscillator simulation

Fig 2.8 Complementary cross-coupled oscillator without resonator

In Fig 2.8, this structure is proposed by Asad A. Abidi in 2001 [10].。 In this structure Asad A. Abidi takes two identical complementary cross-coupled oscillator connected by cross couple, to generate quadrature phase.

Next, we will discuss the symmetric of the QVCO.

V1 V4 V2 V3

V _DD

I tail

V4 V3 V1 V2

V _DD

I tail

V G1 V G2

symmetric

cross-coupling transistor coupling

transistor

cross-coupling transistor coupling

transistor

symmetric (2)

symmetric (1)

(3)

Fig 2.9 QVCO symmetric

In the first option is to couple two identical oscillators in such a way that forces their outputs to oscillate 90

⁰

out of phase, Fig 2.9 shows the typical approach to practically couple two Complementary cross-coupled oscillators.

The second option, a differential output can be provided by coupling two identical

cross-coupled oscillators and sharing source-to-ground of NMOS, as shown on Fig 2.9.

The third option, the complementary cross-coupled oscillator shows a better phase noise performance when compared to the NMOS- or PMOS-only cross-coupled oscillators for the same supply voltage and bias current when operating at the current limited regime. This is mainly because the complementary cross-coupled oscillator of Fig 2.9 presents a larger maximum charge swing q

max

than that of the NMOS- of PMOS-only cross coupled oscillators which overall enhances its phase noise performance, as will be discussed shortly [11] [12].

Next, we will discuss the cross connect of the QVCO.

Fig 2.10 Cross connect of the QVCO.

From Fig 2.10, w e know that how the 2 coupling transistors connect to each other.

In Fig 2.10 (a), first of all, we take two identical Complementary cross-coupled

transistors, place them in the front and back of the block.

In Fig 2.10 (b), second of all, we take two identical Coupling transistors, place them in the left and right of the block

The primary function of the Complementary cross-coupled pair in Fig 2.10 (a) is to generate negative conductance, which eliminates the power dissipation generated by parasitic resistance of the resonator.

On the other hand, QVCO generates differential quadrature topology by utilizing poly-phase filter [10] [13].

Fig 2.11 Classic RC poly-phase filter, shown in two different ways

2-4 PMOS current mirror & output Buffer simulation

Fig 2.12 PMOS 的 current mirror and output buffer schematic

Fig 2.12 prove current mirror and output buffer design mainly, because after the bias voltage of the current mirror is determined, V

G

is setting. And after V

G

is regular, let M5 upper limit in the saturation of buffer be determined. Because, the current of the current mirror influences the amplitude of voltage of the oscillator itself. The lower for V

G3

, then will be big I

D3

, relatively, want let by space on M5 reach saturation getting the less lower [4] [14].

Here, after let Cross couple pair have the largest amplitude swing first, and then come to design and output buffer grade according to the oscillation amplitude at that time, see whether can send the amplitude intact. So, let this current mirror of M3 have the largest bias current first, acted as this current has been determined, indirect V

G3

has been determined.

2-4-1 Bias of the Complementary cross-coupled pair

Fig 2.13 Bias of the Complementary cross-couple pair.

In Fig 2.13 (c), we can write:

1 0

3 − =

− _{SG GS}

DD V V

V

(2-3-3) And

V _{S 3} = V _{S 4}

and

V _{G 3} = V _{D 4}

(2-3-4) So,

4 4

4 3 3

3 S G S D SD

SG V V V V V

V = − = − =

(2-3-5) And

2

1 S

S V

V =

and

V _{G 1} = V _{D 2}

(2-3-6) And

2 2

2 1 1

1 G S D S DS

GS V V V V V

V = − = − =

(2-3-7) We obtain

2 0

4 − =

− _{SD DS}

DD V V

V

(2-3-8) Namely, KVL 2 route of Fig 2.13 (b ), wins the card.

In Fig 2.13 (d), we can write:

2 0

4 − =

− _{SG GS}

DD V V

V

(2-3-9) Also,

V _{S 3} = V _{S 4}

and

V _{G 4} = V _{D 3}

(2-3-10) So, we can write:

3 3

3 4 4

4 S G S D SD

SG V V V V V

V = − = − =

(2-3-11) and

2

1 S

S V

V =

and

V _{G 2} = V _{D 1}

(2-3-12) So

1 1

1 2 2

2 G S D S DS

GS V V V V V

V = − = − =

(2-3-13)

We can obtain

1 0

3 − =

− _{SD DS}

DD V V

V

(2-3-14) Namely, KVL 1 route of Fig 2.13 (b ), wins the card.

When M3=M4、M1=M2 and the same current flows through NMOS and PMOS:

4

3 SD

SD V

V

= 、

V _{DS 1}

=

V _{DS 2}

且

V _{SD 3}

=

V _{DS 1}

、

V _{SD 4}

=

V _{DS 2}

So,

2

DD y x

V V

V = =

have the biggest output voltage swing.

Chapter 3 Phase Noise Analysis

3-1 Introduction

Modern telecommunication system, voltage-controlled oscillators (VCO’s) are an integral part of phase-locked loops, clock recovery circuits, and frequency synthesizers. RF oscillators employed in wireless tranceivers must meet stringent phase noise requirements, typically mandating the use of passive LC tanks with a high quality factor (Q).

3-2 Phase Noise Overview

Fig 3.1 “Perfectly efficient” RLC oscillator.

To simplify matters, assume that the energy restorer is noiseless (see Fig 3.1). The tank resistance is therefore the only noisy element in this model. To gain some useful design insight, first compute the signal energy stored in the tank [12].

2

2 1

pk

stored CV

E =

(3-2-1) so that the mean-square signal (carrier) voltage is

C

V _sig ² = E ^stored

(3-2-2)

where we have assumed a sinusoidal waveform.

Assume that the output in Fig 3.1 is the voltage across the tank, as shown. By postulate, the only source of noise is the white thermal noise of the tank conductance, which we represent as a current source across the tank with a mean-square spectral density of

f kTG i _n

4

2

Δ =

(3-2-3)

For relatively small Δω(called the offset frequency) from the center frequency ω

o

, the impedance of an LC tank may be approximated by

( )

o o o

o

j L Z

ω ω ω ω

ω

+Δ ≈ ⋅ _Δ 2

(3-2-4)

We may write the impedance in a more useful form by incorporating an expression for the unloaded tank Q

GL L

Q R

o

o ω

ω

= 1

= (3-2-5) Solving (3-2-5) for L and substituting into (3-2-4) yields

( )

ω ω ω

ω + Δ = ⋅ Δ Q

Z _o G ^o

2

1

(3-2-6)

Thus, we have traded an explicit dependence on inductance for a dependence on Q and G.

Next, multiply the spectral density of the mean-square noise current by the squared magnitude of the tank impedance to obtain the spectral density of the mean-square noise voltage

⎟⎟ ⎠

⎜⎜ ⎞

⎝

⎛

= Δ Δ ⋅

Δ = ω

ω kTR Q f Z

i f

v _{n n o}

4 2

2 2 2

(3-2-7)

It is traditional to normalize the mean-square noise voltage density to the mean-square

carrier voltage and report the ratio in decibels, thereby explaining the “upside down”

ratios presented previously. Performing this normalization yields the following equation for the normalized single-sideband noise spectral density:

{ }

⎥⎥

⎦

⎤

⎢⎢

⎣

⎡

⎟⎟⎠

⎜⎜ ⎞

⎝

⎛

⋅ Δ

= Δ

2

2 log 2

10

ω

ω ω

Q P

L kT ^o

sig

(3-2-8)

These units are thus proportional to the log of a density. Specifically, they are commonly expressed as “decibels below the carrier per hertz,” or dBc/Hz, specified at a particular offset frequency Δω from the carrier frequency ω

o

.

Leeson

Δω 1 f ³

ω o 2Q

Log(Δω) -3

-2

10·log[(2FkT)/(P sig )]

Eqn. (3-2-8)

Fig 3.2 Phase noise: Leeson versus (3-2-8.)

Even if the output were taken directly from the tank, any resistance in series with either the inductor or capacitor would impose a bound on the amount of filtering provided by the tank at large frequency offsets and thus ultimately produce a noise floor. Last, there is almost always a

( )

Δ

ω

¹

³

region at small offsets (we will ignore here the eventual flattening of the spectrum at extremely small offsets) [15].

A modification to (3-2-8) provides a means to account for these discrepancies

{ }

⎪

⎭

⎪⎬

⎫

⎪⎩

⎪⎨

⎧

⎟⎟

⎟⎟

⎠

⎞

⎜⎜

⎜⎜

⎝

⎛ Δ Δ

⎥ +

⎥

⎦

⎤

⎢⎢

⎣

⎡

⎟⎟⎠

⎜⎜ ⎞

⎝

⎛ + Δ

=

Δ

ω

ω ω

ω ω ³

2 1

2 1 2 1

log

10

^{o f}

sig Q

P

L FkT

(3-2-9)

These modifications, due to Leeson, consist of a factor F to account for the increased noise in the

( ) Δ ω ^{1 2}

region, an additive factor of unity (inside the braces) to account for the noise floor, and a multiplicative factor (the term in the second set of parentheses) to provide a

( )

Δ

ω

¹

³

behavior at sufficiently small offset frequencies.

With these modifications, the phase-noise spectrum appears as in Fig 3.2.

3-3 Phase Noise in VCOs

When VCO phase-noise performance is reported, it is typically measured at only one point in the tuning range. However, the phase noise of on-chip designs is not necessarily constant over the tuning range. Unfortunately, on-chip varactors have a nonlinear C-V curve, and this can make the phase noise over the tuning range nonuniform. Any noise on the control line can lead to additional phase noise as shown in [15], however, any noise generated by the VCO at the varactor terminals will also modulate the carrier and create additional phase noise. This term can be added to the well know Leeson’s formula [9] to take this additional noise mechanism into account.

( )

⎪⎭

⎪ ⎬

⎫

⎪⎩

⎪ ⎨

⎧

⎟⎟ ⎠

⎜⎜ ⎞

⎝ + ⎛

⎥ ⎦

⎢ ⎤

⎣

⎡

⎟⎟ ⎠

⎜⎜ ⎞

⎝

⎛ +

⎟⎟ ⎠

⎜⎜ ⎞

⎝

= ⎛

2 2

2 2 1 1

2 log 2

10 ,

m m VCO m

c s

m o VCO

m f

V K f

f P

FkT Qf

K f f

L

_(3-3-1)

where

L(f

m

,K

VCO

) phase noise in dBc/Hz;

f

o

frequency of oscillation in Hz;

f

m

frequency offset from the carrier in Hz;

F noise figure of the transistor amplifier;

k Boltzmann’s constant in J/K;

T temperature in K;

P

s

RF power produced by the oscillator in W;

f

c

flicker noise corner frequency in Hz;

K

VCO

gain of the VCO in Hz/V;

V

m

total amplitude of all low frequency noise sources in V/Hz;

Since the varactor is nonlinear, K

VCO

varies over the tuning range. Therefore, in some circumstances, the phase noise in the oscillator can be completely determined by the low-frequency noise. At the bottom of the tuning range where the VCO has a high gain, the low-frequency noise dominates. Conversely at the top of the tuning range where the gain is small, the Leeson’s-style noise dominates and determines the phase noise of the oscillator. Thus, the designer must be very careful to minimize these low-frequency noise sources as well as maximizing the Q of the oscillator tank. Note that the varactor can be forward-biased at the top and bottom of its signal swing, but this excess phase noise has nothing to do with forward-biasing the varactor (very little phase noise is generated there regardless) or reducing the varactor’s high-frequency Q due to forward-biasing. This same variation can be demonstrated in simulation using an ideal voltage-controlled capacitor if the C-V characteristics match those of a real varactor. Note also that the excess gain term sometimes included in Leeson’s formula has been ignored. This term, used to model nonlinearities that can contribute to the noise through nonlinear mixing of higher frequency noise around the carrier, is not significant if the oscillator is designed to have very little excess gain, as is the case here [16] [17].

3-4 Quadrature generations

Fig 3.3 Quadrature-coupled LC VCO. (a)Circuit topology; (b)Block diagram.

Quadrature components of a VCO output are needed in nost receivers and transmitters for vector modulation and demodulation and image rejection. The phase and amplitude accuracy of these outputs is critical to the performance of such systems.

There are several options for on-chip quadrature signal generation.

The output of the VCO is applied to a polyphase filter. A polyphase filter is an RC-CR network that in the ideal case shifts its outputs by ±90

⁰

with respect to one another. Unfortunately, this phase shift occurs only in a narrow frequency range and the accuracy of the in-phase and quadrature signals is strongly dependent on the on-chip component matching. Although cascading several stages of stagger-tuned polyphase filters can alleviate this problem, unwanted additional loss is added, requiring amplifiers/buffers to compensate for loss of the filter, at the extra penalty of

higher power consumption [11] [18].

Fig 3.3(b)depicts the block diagram of the circuit shown in Fig 3.3 (a). The four output nodes, namely I

⁺

, Q

⁺

, I

^-

, and Q

^-

, have the same amplitude and frequency but are shifted 90

⁰

out of phase, respectively. The solid triangles signify the cross-coupled pair of NMOS transistors, while the hollow triangles denote the coupling transistors between the two oscillators. Under normal operation conditions, the cross-coupled transistors operate fully switching and provide 180

⁰

phase shift from input to output [solid triangles, Fig 3.3 (b)]. Due to the symmetry of the circuit configuration and as the oscillator would oscillate in the state of equilibrium, the coupling transistors [hollow triangles, Fig 3.3 (b)] operate providing a 90

⁰

phase shift between the input to output. In other words, for instance, if one assumes that the oscillator on the left-hand side is 90

⁰

+ Δ ahead of the one on the right, one can argue that looking at the mirror image of the oscillator we will see that the left-hand side is 90

⁰

- Δ ahead. Assuming that both sides are identical, we should have 90

⁰

+ Δ = 90

⁰

– Δ and thus Δ = 0 [19]

[20].

Chapter 4 Design of the QVCO

4-1 Introduction

Fig 4.1 Quadrature voltage-controlled oscillator schematic

Fig 4.1 shows a 5-GHz Quadrature VCO circuit. It consists of four main parts: a source of negative transconductance (g

m

), an LC-tank circuit, a current source, and output buffers.

4-2 QVCO design follow

Fig 4.2 QVCO design follow

(1)Determine the oscillation frequency and satisfied IEEE 802.11a low and middle band. Modulate inductance and capacitance to achieve high Q characteristic of the resonator.

(2)Determine the PMOS and NMOS size and satisfied the lowest noise figure (NF).

(3)Determine the bias circuit and output buffer.

(4)check performance (5)Layout

(6)LPE

(7)re-simulation (8)Tapeout

4-3 QVCO simulation

4-3-1 Resonator simulation

We obtain the higher Q resonator, so we prior the Q of one inductor:

m27 freq=

m27=7.018 x=115.000000

12.00GHz m28 freq=

m28=8.763 x=105.000000

12.00GHz m29 freq=

m29=10.645 x=95.000000

12.00GHz m30 freq=

m30=12.599 x=85.000000

12.00GHz m27 freq=

m27=7.018 x=115.000000

12.00GHz m28 freq=

m28=8.763 x=105.000000

12.00GHz m29 freq=

m29=10.645 x=95.000000

12.00GHz m30 freq=

m30=12.599 x=85.000000

12.00GHz

2 4 6 8 10 12 14 16 18

0 20

10 15

5 18

freq, GHz

Q2

m27 m28 m29 m30

x=rad=65um~115um higher rad, lower inductance

Fig 4.3 Q of the inductor.

In Fig 4.3, rad represents the radius of the inductor. A large radius has a large inductance (radius: m27 > m28 > m29 > m30). A large inductance has a low Q factor.

In order that increase Q of the resonator, we to try increase Q of the inductor best.

C C_Buffer C=0.2224 pF

C C_cross_couple_pair C=0.085 pF

TSMC_CM018RF_NMOS_RF M2

nr=64 w r=8 um lr=0.5 um Type=1.8V triple-w ell TSMC_CM018RF_NMOS_RF

M1

nr=64 w r=8 um lr=0.5 um Type=1.8V triple-w ell

DC_Feed DC_Feed1

V_DC SRC1 Vdc=0.9 V

VAR VAR1 vtune=0.96

EqnVar

DC_Feed DC_Feed3 V_DC SRC3 Vdc=0.9 V TSMC_CM018RF_JUNCAP_W40 D3

nr=jv

V_DC SRC2 Vdc=vtune V

DC_Feed DC_Feed2 TSMC_CM018RF_JUNCAP_W40 D1

nr=jv TSMC_CM018RF_INDS3_SYM L4

lay=6 rad=x um nr=2 w =30 um

TSMC_CM018RF_INDS3_SYM L5

lay=6 rad=x um nr=2 w =30 um

VAR VAR3 jv=18 x=128

Eqn Var

DC_Feed DC_Feed4 V_DC SRC4 Vdc=1.8 V

Term Term1 Z=50 Ohm Num=1

TF TF1 T=1.00

m18 indep(m18)=

m18=2.503E-11 5.145E9 m18 indep(m18)=

m18=2.503E-11 5.145E9

2. 0 E 9 4. 0 E 9 6. 0 E 9 8. 0 E 9 1. 0 E 10 1. 2 E 10 1. 4 E 10 1. 6 E 10 1. 8 E 10

0. 0 2. 0 E 10

-4E-10 -3E-10 -2E-10 -1E-10 0

-5E-10

1E-10 m18

indep(slope)

sl op e

Eqn k2=m18*(19.7192*indep(m18)) indep(k2)

5145000000.000000 k2

2.539599

(a) (b)

Fig 4.4 (a) The resonator of VCO in this work. (b) Q of the resonator.

Before designing the resonator, it is known that oscillation frequency is decided by total inductance of the resonator and total capacitance, in addition, this circuit uses the varactor to reach the specification that the voltage control oscillation frequency, so preserve oscillation frequency in 5.15GHz.

VAR VAR1 vtune=1

Eqn Var

VAR VAR3 jv=43 x=128

Eqn Var

DC_Feed DC_Feed1

V_DC SRC1 Vdc=0.9 V

DC_Feed DC_Feed3 V_DC SRC3 Vdc=0.9 V TSMC_CM018RF_JUNCAP_W40 D3

nr=jv

V_DC SRC2 Vdc=vtune V

DC_Feed DC_Feed2 TSMC_CM018RF_JUNCAP_W40 D1

nr=jv

TSMC_CM018RF_INDS3_SYM L5

lay=6 rad=x um nr=2 w=30 um TSMC_CM018RF_INDS3_SYM L4

lay=6 rad=x um nr=2 w=30 um Term

Term1 Z=50 Ohm Num=1

TF TF1 T=1.00

m18 indep(m18)=

m18=1.635E-11 5.155E9 m18 indep(m18)=

m18=1.635E-11 5.155E9

2.0E9 4.0E9 6.0E9

0.0 7.0E9

-4E-10 -3E-10 -2E-10 -1E-10 0 1E-10

-5E-10 2E-10

m18

indep(slope)

slo pe

Eqn k2=m18*(19.7192*indep(m18)) indep(k2)

5155000000.000000

k2 1.662296

(a) (b)

Fig 4.5 (a) Traditional resonator structure. (b) Q of the traditional resonator.

Right compared with Fig. 4.5 by Fig. 4.4, in the same inductance value, 2.539 of the

resonant is higher than traditional resonant by 1.662 after improving.

The resonant after improving has three advantages :

[1] Because inductor is not a symmetrical component, symmetry difference of the resonant structure after so relatively Fig. 4.4 is improved for the law of receiving of the traditional resonant cavity of Fig. 4.5 (a), improve resonant after to it constrains to be can restrain harmonic.

[2] Can know in Fig. 4.6, the characteristic with high qualitative factor of resonant originally designed, so relatively high frequency in the adjustable range is taken, the resonant after improving can get a lower phase place .

[3] In the resonant originally designed, two NMOS capacitor contact in series, and connect with the resonant in parallel. NMOS capacitor works in Accumulation region, as the little noise voltage in the varactor and NMOS capacitor [16] [17].

The change of the voltage correctly of NMOS capacitor is contrary to change of the voltage of varactor (as Fig. 4.7 shows). Therefore reduce FM of the noise, in order to reduce the phase noise.

m18 indep(m18)=

m18=2.588E-11 5.255E9 m18 indep(m18)=

m18=2.588E-11 5.255E9

5.0E9 7.0E9

-3E-10 -2E-10 -1E-10 0

-4E-10 1E-10

m18 indep(m18)=

m18=2.709E-11 5.355E9 m18 indep(m18)=

m18=2.709E-11 5.355E9

5.0E9 7.0E9

-3E-10 -2E-10 -1E-10 0

-4E-10 1E-10

m18 indep(m18)=

m18=2.467E-11 5.155E9 m18 indep(m18)=

m18=2.467E-11 5.155E9

5.0E9 7.0E9

-4E-10 -3E-10 -2E-10 -1E-10 0

-5E-10 1E-10

indep(slope)

sl op e

m18

Eqn k2=m18*(19.7192*indep(m18)) indep(k2)

5155000000.000000 k2 2.507286

indep(slope)

sl op e

m18 _m18

indep(slope)

sl op e

Eqnk2=m18*(19.7192*indep(m18)) Eqn k2=m18*(19.7192*indep(m18)) indep(k2)

5255000000.000000 k2 indep(k2)

5355000000.000000 k2

2.681412 2.860689

(a) (b) (c)

Fig 4.6 (a)f=5.15GHz (b)f=5.25GHz (c)f=5.35GHz

m34 indep(m34)=

m34=3.608E-13 freq=5.150000GHz

1.800 m35

indep(m35)=

m35=3.016E-13 freq=5.150000GHz

1.800 m34 indep(m34)=

m34=3.608E-13 freq=5.150000GHz

1.800 m35

indep(m35)=

m35=3.016E-13 freq=5.150000GHz

1.800

1.5

1.0 2.0

2.8E-13 3.8E-13

_20050823_ind_C_jv..vtune

_2 005 0823 nd_C_j v. .C y _i

m35

vd

Cy

m34 NMOS capacitor

junction varactor

Fig 4.7 NMOS capacitor and varactor versus vtune.

4-3-2 Complementary cross-coupled oscillator simulation

Because complementary cross-coupled pair offers negative conductance mainly, and noise include flicker noise, shot noise, thermal noise that the initiative component generate. Hence, we are choosing NMOS and PMOS of the cross-coupled pair, will consider according to the size of noise figure of transistor.

And then, noise figure of simulation NMOS and PMOS transistors.

m1 indep(m1)=

m1=7.392 freq=5.250000GHz

19.000 m1 indep(m1)=

m1=7.392 freq=5.250000GHz

19.000

10 20 30 40 50 60

0 70

8 10 12 14 16

6 18

aa15..SP.x

aa 15. .nf (1)

m1

aa25..SP.x

aa 25. .nf (1)

aa35..SP.x

aa 35. .nf (1)

aa45..SP.x

aa 45. .nf (1)

SP.x

nf (1)

aa65..SP.x

aa 65. .nf (1)

aa75..SP.x

aa 75. .nf (1)

aa80..SP.x

aa 80. .nf (1)

NMOS-RF length=0.18um

watch frequency=5.25GHz nf(1) of NMOS-RF V.S

nr=1~64

@wr=1.5um~8um sweep

(a)

m1 indep(m1)=

m1=7.392

freq=5.250000GHz 0.180

m2 indep(m2)=

m2=13.399

freq=5.250000GHz 0.500 m1 indep(m1)=

m1=7.392

freq=5.250000GHz 0.180

m2 indep(m2)=

m2=13.399

freq=5.250000GHz 0.500

0.20 0.25 0.30 0.35 0.40 0.45

0.15 0.50

8 10 12

6

14 m2

NMOS noise figure

@wr=1.5um & nr=19 watch

length:0.18um~0.5um

SP.x

nf (1)

m1

(b)

Fig 4.8 (a)NF versus nr of NMOS; (b)NF versus length of NMOS

In Fig. 4.8 (a ), we can see wr and nr of NMOS transistor, the relation between it and noise figure, then we get, in nr =19 and wr =1.5, there is minimum noise figure. And

then can know that the bigger length is , noise figure is the bigger by Fig. 4.8 (b).

PMOS Length:0.18um sweep:wr=1.5um~5.5um nr=1~64

m2 indep(m2)=

m2=4.397 freq=5.250000GHz

64.000 m4 indep(m4)=

m4=10.698 freq=5.250000GHz

10.000

m6 indep(m6)=

m6=5.963 freq=5.250000GHz

37.000

m1 indep(m1)=

m1=3.546 freq=5.250000GHz

0.500 m3 indep(m3)=

m3=3.546 freq=5.250000GHz

0.500

m5 indep(m5)=

m5=3.546 freq=5.250000GHz

0.500

m7 indep(m7)=

m7=3.546 freq=5.250000GHz

0.500

m2 indep(m2)=

m2=4.397 freq=5.250000GHz

64.000 m4 indep(m4)=

m4=10.698 freq=5.250000GHz

10.000

m6 indep(m6)=

m6=5.963 freq=5.250000GHz

37.000

m1 indep(m1)=

m1=3.546 freq=5.250000GHz

0.500 m3 indep(m3)=

m3=3.546 freq=5.250000GHz

0.500

m5 indep(m5)=

m5=3.546 freq=5.250000GHz

0.500

m7 indep(m7)=

m7=3.546 freq=5.250000GHz

0.500

10 20 30 40 50 60

0 70

5 10 15

0 20

bb15..SP.x

bb1 5. .nf (1) m4

m6 m2

bb25..SP.x

bb2 5. .nf (1)

bb35..SP.x

bb3 5. .nf (1)

bb45..SP.x

bb4 5. .nf (1)

bb55..SP.x

bb5 5. .nf (1)

bb65..SP.x

bb6 5. .nf (1)

bb75..SP.x

bb7 5. .nf (1)

bb80..SP.x

bb8 0. .nf (1)

m1 m3 m5 m7

(a)

m1 indep(m1)=

m1=1.760

freq=5.250000GHz 0.180 m1 indep(m1)=

m1=1.760

freq=5.250000GHz 0.180

0.20 0.25 0.30 0.35 0.40 0.45

0.15 0.50

2.0 2.5 3.0 3.5

1.5 4.0

SP.x

nf (1)

m1

PMOS wr=8um nr=64um

length:0.18um~0.5um

(b)

Fig 4.9 (a)NF versus nr of PMOS; (b)NF versus length of PMOS

In Fig 4.9 can know , width of the same PMOS, width =wr *nr, the wr is smaller, noise figure is the lower. So, the relation determines size of NMOS and PMOS according to this finally.

In decide complementary cross-coupled pair and after adding resonator, because complementary cross-coupled pair has parasitic capacitance, so will increase capacitance of total in resonator, will cause oscillation frequency to drop, while fine tune. Behind is it produce to ask parasitic capacitance of complementary cross-coupled pair again, is it answer to take the place of resonator to fine tune.

4-3-3 PMOS current mirror & output Buffer simulation

785 mV vin 1.02 V VG 1.80 V

1.80 V 1.80 V 1.80 V 1.80 V

0 V vout

0 V 1.51 V VD 1.51 V

VAR VAR2

down_nr=64 down_wr=8 down_lr=0.18

Eqn Var

VAR VAR1

up_nr=64 up_wr=8 up_lr=0.18

Eqn Var

0 A VtSine

SRC2

Phase=0 Damping=0 Delay=0 nsec Freq=5.25 GHz Amplitude=0.666 V Vdc=0.785 V -292 uA 292 uA

-292 uA 292 uA TSMC_CM018RF_PMOS_RF M1

nr=10 wr=1.5 um lr=0.18 um Type=1.8V twin-well

0 A R R1 R=50 Ohm

-8.98 mA 8.98 mA

-8.98 mA 0 A

TSMC_CM018RF_PMOS_RF M3

nr=down_nr wr=down_wr um lr=down_lr um Type=1.8V twin-well

0 A DC_Block DC_Block1 292 uA

-292 uA -292 uA 292 uA

TSMC_CM018RF_NMOS_RF M4

nr=1 wr=1.5 um lr=0.18 um Type=1.8V triple-well

-9.27 mA V_DC

SRC1 Vdc=1.8 V

8.98 mA I_Probe ID3_up

8.98 mA I_Probe ID4_down -8.98 mA 8.98 mA

-8.98 mA 0 A

TSMC_CM018RF_PMOS_RF M2

nr=up_nr wr=up_wr um lr=up_lr um Type=1.8V twin-well

Fig 4.10 Simulation of output buffer

Fig 4.11 Input waveform of output buffer.

Fig 4.12 Output waveform of output buffer.

After swing that the waveform can be intact, we can take the place of it while entering the intact circuit, then fine tune Performance.