CHAPTER 4 ELECTRONICS CIRCUIT
4.4 Detection Modes
The driving electrodes and sensing electrodes are arranged as shown in Fig. 4.14(a). A driving electrode places opposite to a sensing electrode.
The driving electrodes are separated with sensing electrodes. Because the electrostatic force is always attractive, the electrodes should be balance placed to enlarge the sensing range. As shown in Fig. 4.14(b), the electrodes D1, D2, and D4 are used to form the control loop. When the acceleration is positive to the x-axis, the voltage of D1 rises to pull the
ring back to the neutral position. When the acceleration is negative, D4 is accompanied with D2 to pull back the ring. Similar mechanism is used on y-axis. The summary of the rebalance force on electrodes for the acceleration is listed in Table 4.The feedback voltage signal in the closed-loop stands for the amplitude of the linear acceleration.
The structural displacement is caused both by linear acceleration and Coriolis force. As shown in Fig. 3.4, both linear acceleration and flexural vibration induce the displacement of the main ring of the structure. The displacement is expressed as follows.
t r
t X
S = cosω + cosωn , (4-22)
where X is the amplitude induced by linear acceleration, ω is the acceleration frequency, r is the amplitude of the flexural vibration, and
ω is the natural frequency of the structure. The frequency range of the n
acceleration is from zero to 50Hz, and the natural frequency of the structure is 20K Hz. These two frequencies are far away and can be separated with filters. Higher order filter is used for boarder range of the acceleration.
The sensing coupling of the acceleration and rotation leads to the signal coupling, and force to rebalanced mode is used to eliminate this effect. The closed loop control is used for this purpose, and it has fast time response of signal. Figure 4.15 shows the concept. An extra force f1 applies on the structure and induces the displacement. The rebalanced force f2 feeds back to the structure according to the induced displacement.
The PI control is used for the zero steady-state error.
Figure 4.16 shows the applying forces and corresponding displacements under second mode. The input force is sinusoidal force with unit magnitude and zero-phase. Assume the input frequency is close
fa
to the natural frequency, the response displacement xa is K
Q and the
lagged phase is ) (−π2 +θa and the phase lag is the same as which of . The corresponding displacement induced by is . The magnitude of is
fb fb Ω va
va
fb xb xb ( )2ωΩ
K
Q . When
the natural frequencies of two modes are identical, the phase lag of is
xb
) 2 2
(−π + θa
. Applying phase-locked loops to the driving circuit can effectively eliminate the phase lagθa, because it will actually track the phase at
2
− . If we use open-loop mode to detect the rotation rate, the π
ratio betweenxa andxb is expressed as follows.
If we use force-to-rebalance mode to detect the rotation rate, the ratio between fa and fb is expressed as follows.
Obviously, two expressions are similar. The magnitude ofxb is( )2ωΩ K
Q ,
that stands for the induced displacement will be magnified by quality factor and reduced by structural stiffness. Under slight damping condition, open-loop mode is preferred. Under atmosphere, the quality factor for the micro structure presented in this dissertation possibly is less than 10.
Moreover, if the natural frequencies of two modes are not identical, the
There exists an extra phase lag due to the different natural frequencies of two modes. The ratio between and remains simple expression as Eq.
(4-25). Thus, force-to-rebalance mode is preferred. Table 5 lists the summary of applying forces and corresponding displacements under second mode.
fa fb
4.5 Scheme for Detecting Rotation and Acceleration
When both the main ring and support rings of the sensor are considered, the governing equation of the n-th mode vibration is represented as follows.
⎪⎩
&& & & &
&&
2
2 , (4-26)
where A is the effective mass; B and are the effective masses associated with the Coriolis force; c is the effective damping; C is the effective stiffness; and are the generalized forces, and and
are generalized coordinates of the nth mode of vibration.
B2
an
F Fbn an
bn
This work addresses the first and second modes. The first mode involves linear acceleration, and the second involves rotation. The rebalancing loop for detection is added to sense the rotation without which the signal process would be much more complex. Based on Eq. (4-26), with reference to the second mode but ignoring the angular acceleration, the driving forces are as follows.
⎪⎩
where ω is the natural frequency of the second mode and equals C A and K is gain of the rebalancing force which is exerted by the rebalancing loop. The output signal determined by the rebalancing loop is,
c t Kb B
Vrot = 2 = −Ω sinω . (4-28)
The output voltage is proportional to the rate of rotation. This finding is obtained by setting a large gain of rebalancing force, making much smaller than in Eq. (4-26), such that the terms in can be neglected.
It also eliminates the effect of angular acceleration. Figures 3.8(a) and 3.8(b) depict the detection scheme used to measure the rate of rotation.
The fixed amplitude of the primary mode is driven in and the Coriolis force induces a response in the secondary mode in .
b2
a2 b2
a2
b2
The first mode of vibration is rebalanced by two rebalancing loops to sense linear accelerations. The amplitude of induced displacement is constrained by the applied force, the driving frequency, effective stiffness, and gain of the rebalancing force. When the driving frequency is much smaller than the resonant frequency of the first mode, the amplitude and the output voltage are approximated to,
⎪⎩
The effective stiffness is designed to be high to reduce the amplitude as much as possible. Also, the rebalance loop is added to yield the readout circuit. Figures 3.8(c) and 3.8(d) present the detection scheme for sensing
acceleration. The opposing support rings are displaced equally when the structure is accelerated. The difference between the induced signals of the displacements of the opposing support rings represents the linear accelerations.
4.6 Theoretical Errors
The sources of theoretical errors discussed herein include the shifting of the natural frequency and angular acceleration. The structure is designed to vibrate at its resonant frequency, is close to the natural frequency if damping is weak. The factors that influence the resonant frequency must be considered. The first one is damping. Providing a stable environment in which the sensor can operate is a solution.
Acceleration is one primary factor that influences the natural frequency.
Theoretically, a force or acceleration causes the natural frequency to drift, governed by,
EIn F r
n ⋅ ⋅
=
∆ 22 2
ω π
ω . (4-30)
According to the simulation results, this drift is neglectable. This effect depends on the ratio of the applied force to the relative stiffness of the structure. In this work, this ratio on the micro scale is too small to have any effect.
Equation (4-26) specifies the errors due to the angular acceleration.
As mentioned, the sensor incorporates designed rebalancing loops. A steady state error actually occurs in the rebalancing loops. This error is simply treated as a constant force applying to the structure. Equation (4-26) for the second mode of vibration is solved as follows;
b
When a force is applied, an angular acceleration causes the force in a single direction to have an unwanted influence on another direction, generating noise. Applying a sinusoidal force also creates this problem.
Increasing the effective stiffness and the gain of the rebalancing force can solve it. However, an excessive effective stiffness makes the natural frequency of the structure extremely high, which leads to a high working point of the circuit. A better alternative is to increase the gain of the rebalancing force.
Chapter 5 Structural Fabrication and Preliminary Test
In general, silicon micro-machining processes for fabrication of vibratory gyroscopes fall into one of four categories: 1) silicon bulk micromachining and wafer bonding; 2) poly-silicon surface micromachining; 3) metal electroforming and LIGA; and 4) combined bulk surface micromachining or so-called mixed processes [87]. The process proposed in this chapter falls in to the first category. The fabrication is based on the deep silicon etching and wafer bonding. An aspect ratio dependent effect (ARDE) always occurs in the dry etching process for a MEMS device. Three sets of processes are developed and modified progressively for eliminating ARDE from the fabrication results.
Results indicate that the proposed process provides more flexibility than other processes with respect to the structural fabrication of a MEMS device. The sensitivity of the sensor characteristic to the manufacturing errors is considered as well. Preliminary test results are also presented.
5.1 Brief of Process Technologies
The deep silicon etching used in this dissertation is executed with inductive coupled plasma (ICP). Two sets of RF power unit provide high-density plasma and isotropic etching. With this setting, the effective plasma area locates middle of the chamber and does not damage the chamber surface. It also decoupled the effects for two independent power sources. The primary etchants are SF6 and C4F8. The original etchants
are SF6 and oxygen, and the later is the sidewall passivating gas. The sidewall etching simultaneously happens and the protection is required to provide better slope. With oxygen adding, the silicon dioxide recombines and deposits on the surface including sidewall and bottom [88,89]. An alternative is to provide the passivation from C4F8. With C4F8, the thin Teflon like passivation layer deposites on the wafer, including the bottom and the sidewall of previously etched hole during the process.
Significantly higher aspect ratios are achieved by using a time-multiplexed process, which continuously switches between passivation and etching steps. This method works for this scale but not for narrower gap to 0.1um. The reason comes from the thickness of the polymer. For the scale of sub-micron, the influence from the polymer is comparable with gap itself. The chlorine etching is a possible solution. The possible damages from the ICP dry etching process are electrical and mechanical influence. Electrically, the plasma may damage the threshold voltage of the p-n junction and the breakdown of the gate oxide. The circuit component is not implemented on the structure, and it does not affect the design. The process quiet often induces the structural damage for III-V but not for silicon. Especially, the desired material is silicon wafer and it inherits the crystalline structure even processed. Some experiment shows that the high-density plasma caused low stress and damage during the process relative to other fabrication process [90].
The dry etched silicon wafer and the glass wafer are bonded with anodic bonding technique. This process is accomplished with anodic bonder. The bonding temperature is 380ºC and the bonding voltage is 500 volt. Generally speaking, the anodic bonding technique is used to bond the silicon and glass, and it is a mature technique that required simple equipment setup. Anodic bonding relies on charge migration to produce bonded wafers. This usually involves a silicon wafer and a glass wafer
with a high content of alkali metals [91]. For instance, Pyrex borosilicate glass, a typical material for this application, has a sodium oxide (Na2O) content of 3.5%. In this approach, the presence of mobile metals is exploited by applying a high negative potential to the glass to attract the positive ions (Na+) to the negative electrode, where they are neutralized [92]. Such a removal permits the formation of a space charge at the glass-silicon interface, which creates a strong electrostatic attraction between the silicon and the glass wafers that holds both pieces firmly in place.
This technique has been reported as producing uniform bonds; however, the presence of charge carriers makes this bond generally not compatible with active devices. The bonding process increases the leakage current for CMOS process [94]. The technique, originally proposed by Wallis and Pomerantz [95], has been used for pressure sensor, solar cell, and piezoresistive applications, as well as for packaging. A novel application which involves with anodic bonding, was presented in 1997 by Robert Bayt [96]. Moreover, the structure fabricated with anodic bonding can withstand a chamber pressure up to 1000 psi. This process does not involve many problems for mechanical property.
The structure is dumped into the KOH to etch the upper layer of silicon. The composition of the KOH solution should be taken care about the relative etching rate for silicon to oxide. The desired condition for KOH is 10%wt and 60ºC that implies the ratio to 1000[97]. An alternative etchant is TMAH which provides very high etching selectivity for silicon to oxide [103,104]. Moreover, both using of KOH and TMAH require a stable environment to insure the liquid concentration remains constant.
5.2 Fabrication Process
The device can be fabricated in numerous ways. Silicon bulk micromachining and wafer bonding technologies are used in this work follow from the structural design and the capacitive detection scheme.
The main frame of the structure sits on the plane of the silicon wafer. The structural stiffness along the z-axis should be as large as possible to minimize the coupling of vibrations along different axes. Hence, deep silicon etching is used to form a bulk structure. Besides, detecting and driving schemata, based on the electrostatic force, would be more effective for relatively large capacitances. A larger capacitance corresponds to a deeper structure. Deep silicon etching technique for forming high-aspect-ratio structures must be used to ensure good detection performance. Anodic bonding is utilized to bond the silicon to the glass. It is a mature technique and is used herein to create the suspended structure.
Three processes are developed for fabricating the structure of the motion sensor. They are modified to reduce the ARDE and are described as follows. The process described in the following sections is observed along AA' indicated in Fig. 4.1(a).
Figure 5.1 shows the first method of fabricating the sensor. The process begins with a {1, 0, 0} n-type silicon wafer, which is patterned using photo resist, as depicted in Fig. 5.1(a). The patterned wafer is etched with deep silicon etching by ICP etcher, as depicted in Fig. 5.1(b).
The etched silicon wafer is bonded to a glass wafer by anodic bonding, as depicted in Fig. 5.1(c). The upper part of the composite wafer is removed by back-sided wet etching and the structure is formed, as indicated in Fig.
5.1(d). The structure is then released by wet etching the glass wafer, as indicated in Fig. 5.1(e). Ideally, the etching rate is uniform at every
position on the wafer. During deep etching, the RIE lag appears in the narrow trench. This effect is known as the aspect ratio dependent effect (ARDE). Figure 5.1(b) plots the RIE lag in the capacitor gap. The capacitor gap is 2 µm wide, as shown in Fig. 4.1(a). During the wet etching of the backside, some part not on the capacitor gap will be etched through first, as presented in Fig. 5.1(d). Intuitively, etching could be continued through the gap. However, this aforementioned structure has a high aspect ratio. Etching through the silicon wafer causes permanent damage to the wall of the structure. The structure will not be released until the removal of the RIE lag part of the structure, as depicted in Fig.
5.1(e). Figure 5.2(a) presents the side view of the unreleased structure, which has formed a 100µm-high wall. Reducing the etching depth reduces ARDE and the RIE lag. Figure 5.2(b) presents the structure with a 20µm-high wall. However, the final structure is not sufficiently strong to prevent structural warping. The ARDE is negligible for the designed 20µm-high structure.
An alternative means (method II) of modifying the process is to add a protective layer and dummy fields. Figure 5.3 schematically describes method II. The dummy field can be used to reduce the RIE lag in dry etching, as plotted in Fig. 5.3(b). The RIE lag is not entirely eliminated, because the dummy field should be sized so as not to affect the performance of the sensor. Hence, the gap between the structure and the dummy field is wider than that between the structure and the electrode.
The protective layer is added after dry etching and before anodic bonding, as depicted in Fig. 5.3(c). This protective layer must be suitable to undergo the anodic bonding process. Hence, oxide and nitride are the candidate materials for this layer. This layer will protect the wall of the structure as long as the silicon is etched through in a back-sided wet
etching process. The protective layer should resist the etchant until the RIE lag part is removed. The etchant used in wet etching must be isotropic. The height of the structure can be estimated from the following formula.
where H is the height of the structure; t is the thickness of the protective layer; is the selectivity of the etchant, and is the RIE lag ratio.
The protective layer used in this case is nitride, and its thickness is 2000Å.
A thicker layer does not favor anodic bonding. The etchant used is HNA.
The etching selectivity is 60. The dummy fields reduce the RIE lag ratio to 0.2. The height of the structure with the protective layer is estimated to be up to 40µm, when the protective layer is included. When the protective layer is etched away and the silicon is exposed, as described above, etching can be performed 20µm more deeply, without being affected by the ARDE. Hence, a 60µm (40µm + 20µm) structure is accordingly fabricated, and is presented in Fig. 5.4.
S LRIE
The third method improves upon method II. The dummy field is sized to equalize the widths of all trenches (gaps) on the wafer, effectively eliminating ARDE and the RIE lag, as presented in Figs. 5.5(a) and 5.5(b). Unlike in method II, the dummy fields must be removed. A 2µm step between the bonding region and non-bonding region is etched before the PR coating process is performed to remove the dummy field, as indicated in Fig. 5.5(a). The dummy field makes negligible RIE lag in the deep silicon etching process. The protective layer is deposited on silicon, as depicted in Fig. 5.5(c), and a 2000Å oxide is used herein. This layer is not necessary but still used for better yield. An inter layer of 5000Å nickel is deposited on the glass wafer. This layer prevents the
bonding of dummy fields to the glass, as indicated in Fig. 5.5(d). It also prevents the bonding of the structure to the glass, ensuring that the structure is ideally released. An anodic bonder is used to bond the silicon wafer and the glass wafer. Back-sided wet etching removes the upper part of the resulting SOI structure, yielding the structure depicted in Fig.
5.5(e). The structure is released by wet etching the glass wafer, as depicted in Fig. 5.5(f). Figure 5.6 presents the resulting structure, whose height is 180µm, which is satisfactory [106].
During the removal of the dummy fields, rather than increasing the step height which generates lithographic deficit, the inter layer is introduced between the silicon and the glass in this method. Moreover, anodic bonding can generate a large electrostatic force that collapses the suspended structure. In the absence of an interlayer, the force would pull silicon and glass into contact with each other, causing undesired bonding [105].
There is a parameter, which is not directly involved with the fabrication, but concerned about package. It is quality factor, and it vitally
There is a parameter, which is not directly involved with the fabrication, but concerned about package. It is quality factor, and it vitally