CHAPTER 5 FABRICATION
5.2 Fabrication Process
The device can be fabricated in numerous ways. Silicon bulk micromachining and wafer bonding technologies are used in this work follow from the structural design and the capacitive detection scheme.
The main frame of the structure sits on the plane of the silicon wafer. The structural stiffness along the z-axis should be as large as possible to minimize the coupling of vibrations along different axes. Hence, deep silicon etching is used to form a bulk structure. Besides, detecting and driving schemata, based on the electrostatic force, would be more effective for relatively large capacitances. A larger capacitance corresponds to a deeper structure. Deep silicon etching technique for forming high-aspect-ratio structures must be used to ensure good detection performance. Anodic bonding is utilized to bond the silicon to the glass. It is a mature technique and is used herein to create the suspended structure.
Three processes are developed for fabricating the structure of the motion sensor. They are modified to reduce the ARDE and are described as follows. The process described in the following sections is observed along AA' indicated in Fig. 4.1(a).
Figure 5.1 shows the first method of fabricating the sensor. The process begins with a {1, 0, 0} n-type silicon wafer, which is patterned using photo resist, as depicted in Fig. 5.1(a). The patterned wafer is etched with deep silicon etching by ICP etcher, as depicted in Fig. 5.1(b).
The etched silicon wafer is bonded to a glass wafer by anodic bonding, as depicted in Fig. 5.1(c). The upper part of the composite wafer is removed by back-sided wet etching and the structure is formed, as indicated in Fig.
5.1(d). The structure is then released by wet etching the glass wafer, as indicated in Fig. 5.1(e). Ideally, the etching rate is uniform at every
position on the wafer. During deep etching, the RIE lag appears in the narrow trench. This effect is known as the aspect ratio dependent effect (ARDE). Figure 5.1(b) plots the RIE lag in the capacitor gap. The capacitor gap is 2 µm wide, as shown in Fig. 4.1(a). During the wet etching of the backside, some part not on the capacitor gap will be etched through first, as presented in Fig. 5.1(d). Intuitively, etching could be continued through the gap. However, this aforementioned structure has a high aspect ratio. Etching through the silicon wafer causes permanent damage to the wall of the structure. The structure will not be released until the removal of the RIE lag part of the structure, as depicted in Fig.
5.1(e). Figure 5.2(a) presents the side view of the unreleased structure, which has formed a 100µm-high wall. Reducing the etching depth reduces ARDE and the RIE lag. Figure 5.2(b) presents the structure with a 20µm-high wall. However, the final structure is not sufficiently strong to prevent structural warping. The ARDE is negligible for the designed 20µm-high structure.
An alternative means (method II) of modifying the process is to add a protective layer and dummy fields. Figure 5.3 schematically describes method II. The dummy field can be used to reduce the RIE lag in dry etching, as plotted in Fig. 5.3(b). The RIE lag is not entirely eliminated, because the dummy field should be sized so as not to affect the performance of the sensor. Hence, the gap between the structure and the dummy field is wider than that between the structure and the electrode.
The protective layer is added after dry etching and before anodic bonding, as depicted in Fig. 5.3(c). This protective layer must be suitable to undergo the anodic bonding process. Hence, oxide and nitride are the candidate materials for this layer. This layer will protect the wall of the structure as long as the silicon is etched through in a back-sided wet
etching process. The protective layer should resist the etchant until the RIE lag part is removed. The etchant used in wet etching must be isotropic. The height of the structure can be estimated from the following formula.
where H is the height of the structure; t is the thickness of the protective layer; is the selectivity of the etchant, and is the RIE lag ratio.
The protective layer used in this case is nitride, and its thickness is 2000Å.
A thicker layer does not favor anodic bonding. The etchant used is HNA.
The etching selectivity is 60. The dummy fields reduce the RIE lag ratio to 0.2. The height of the structure with the protective layer is estimated to be up to 40µm, when the protective layer is included. When the protective layer is etched away and the silicon is exposed, as described above, etching can be performed 20µm more deeply, without being affected by the ARDE. Hence, a 60µm (40µm + 20µm) structure is accordingly fabricated, and is presented in Fig. 5.4.
S LRIE
The third method improves upon method II. The dummy field is sized to equalize the widths of all trenches (gaps) on the wafer, effectively eliminating ARDE and the RIE lag, as presented in Figs. 5.5(a) and 5.5(b). Unlike in method II, the dummy fields must be removed. A 2µm step between the bonding region and non-bonding region is etched before the PR coating process is performed to remove the dummy field, as indicated in Fig. 5.5(a). The dummy field makes negligible RIE lag in the deep silicon etching process. The protective layer is deposited on silicon, as depicted in Fig. 5.5(c), and a 2000Å oxide is used herein. This layer is not necessary but still used for better yield. An inter layer of 5000Å nickel is deposited on the glass wafer. This layer prevents the
bonding of dummy fields to the glass, as indicated in Fig. 5.5(d). It also prevents the bonding of the structure to the glass, ensuring that the structure is ideally released. An anodic bonder is used to bond the silicon wafer and the glass wafer. Back-sided wet etching removes the upper part of the resulting SOI structure, yielding the structure depicted in Fig.
5.5(e). The structure is released by wet etching the glass wafer, as depicted in Fig. 5.5(f). Figure 5.6 presents the resulting structure, whose height is 180µm, which is satisfactory [106].
During the removal of the dummy fields, rather than increasing the step height which generates lithographic deficit, the inter layer is introduced between the silicon and the glass in this method. Moreover, anodic bonding can generate a large electrostatic force that collapses the suspended structure. In the absence of an interlayer, the force would pull silicon and glass into contact with each other, causing undesired bonding [105].
There is a parameter, which is not directly involved with the fabrication, but concerned about package. It is quality factor, and it vitally affects the sensor performance. With high quality factor, the signal would be magnified and the noise would be suppressed relatively. For the sensor, the quality factor is concerned about structure damping and the viscous damping. The structure damping comes from the silicon itself. Both single and polycrystalline silicon microstructures have shown high mechanical quality factors ( to ) under medium vacuum levels that the pressure is less than 10 milli-torr [98]. In other words, the quality factor is dominated by viscous damping under atmosphere or low vacuum levels. Generally, the viscous damping for the microstructure is classified as lateral damping [99] and squeeze damping [100]. The lateral damping means the damping effect exists at the lateral period relative to the moving direction. It is recognized with Reynold’s Number. The
squeeze-104 106
film damping theory describes about phenomenon that the air is trapped between two parallel plates. It is quite often for microstructure. The condition for the squeeze-film is expressed as the squeeze number. With considering about the sensor for those two damping theories, the quality factor of the structure is 15 under 10 torr. The quality factor required from the design needs more than that, which means a vacuum environment provided by packaging is required. Anodic bonding contains the possibility to provide the package. The glass is used as the substrate and it can be used more. In fact, many designs have taking advantage on anodic bonding to provide vacuum and relative package [101].