Second, detailed poly-Si TFTs fabrication processes and experimental procedure were described.
2.1 Fabrication Process of Poly-Si TFTs
The top gate p-channel and self align light drain doping (LDD) TFTs were fabricated on Corning1737 glass substrate [1]. First, the buffer SiNx/oxide layer and 50 nm thickness a-Si:H film were deposited by plasma enhanced chemical vapor deposition (PECVD) at 380℃, we dehydrogenated aSi:H film in a furnace at 450℃. Then the poly silicon channel was formed by 308nm XeCl excimer laser irradiation at 350mJ/cm2. In this work, 95%
laser overlap ratio was adopted to obtain large grain size and better uniformity of active layer. As the SEM Fig2.1, the average grain size of polycrystalline silicon was found to be 280~300nm [3]. The island was patterned by plasma dry etching Fig2.2. The 100nm thickness gate insulator was deposited by TEOS (Tetra-Ethyl-Ortho-Silicate)-base oxide.
The source/drain and LDD region were formed by the mass-separated ion implanter technique. The doping activation was performed at 530℃/1hr thermal furnace and RTA irradiation Fig2.3~Fig2.5. Finally, the interlayer oxide and inter-connection metal were deposited and pattern. The H2 plasma hydrogenation was performed in a commercial RF parallel-plate plasma reactor at 100W, 480℃ 15min in H2 and Argon gas mixture. The SiO2/SiNx with 300nm and 100nm interlayer film and source/drain contact holes etching and S/D metal patterning Fig2.6. Finally, the planer layer (UHA2) and ITO were employed on our device Fig2.7 [4-6]. The fabrication process of n channel Poly-Si TFTs with lateral body terminal (LBT) are almost the same as n channel LTPS Poly-Si TFTs, The p-doped lateral body terminal is the only different. The fabrication process of LBT TFTs needs no additional mask step. The body terminal was formed by the mass-separated ion implanter technique. The device electrical measurements were finished by HP4156C and Keithley
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4200-SCS.The data of chapter3 were measured by HP4156P, and the data of chapter4 were measured by Keithley 4200.
2.2 Introduction of Instruments
In this thesis, all of the electrical characteristics of proposed poly-Si TFTs were measured by HP 4156B-Precision and Keithley 4200-SCS Semiconductor Parameter Analyzer , illustrated in Fig2.8, a probe station is situated inside a dark box. Many methods have been proposed to extract the characteristic parameters of poly-Si TFTs.The photo leakage current was measured as we putted the device up on back-light. We can change the applied current of back-light to control the brightness. The ground probe station is furnished with an electrically isolated, water-cooled thermal chuck. The chuck is
controlled by Temptronic TPO315A thermal controller, which can operate temperature from 25C to 75C. An Agilent 4156C precision semiconductor parameter analyzer can provide I-V measurement, bias for BTS, and quasi C-V measurement, etc. We employ the ICS (Interactive Characterization Software) to obtain the output and transfer characteristics, like VD-ID, VG-ID (Linear), VG-ID (saturation), and extract the typical semiconductor parameters.
An analyzer Keithley 4200-SCS can do the same analyze like HP4156C.
2.3 Electrical Characterization Measurement and Analysis 2.3.1 Output Characteristics
The typical TFT output characteristics are shown in Fig.2.12. They represent the dependence of the Drain-Source current (IDS) on the Drain-Source voltage (VDS) at different gate voltage (VGS). The Drain-Source current increase linearly at low Drain-Source voltage (Linear regime/operation) and saturates at high Drain-Source voltage (Saturation regime /operation). The saturation values of IDS depend on the applied gate voltage. When the low gate voltage is applied, the thickness of the induced channel is small and current is low. On
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the other hand, thicker channel is induced at high gate voltage and the saturation current is higher. Well-separated output characteristics are an indication of good ohmic contact at drain and source. The transistor enters in saturation regime when VDS >VSAT , where VSAT=VGS-VT . In Id_Vd curve, the points corresponding to VDS = VSAT are connect the blue line described the following equation:
field mobility effect mobility can be determined from measuring the saturation current, plotting the square root of the measured IDS vs. VGS in saturation ( VDS≧VGS-VT ).Of course, the poly-Si TFTs are not perfect device as the single crystalline; it is since the grain boundary [10]. The region of operation in poly-Si TFT roughly:
A. Cut-off : Current is due to reverse-bias drain junction leakage trap-assisted mechanisms.
B. Subthreshold : Current is due to carrier diffusion. Limited by source junction potential
2.3.2 Methods of Device Parameter Extraction
In this section, we will introduce the methods of typical parameter extraction such as the threshold voltage VT, subthreshold swing S.S, field-effect mobility FE from the device
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characteristics.
Several methods are used to determinate the threshold voltage, VT , which is the most important parameter of the semiconductor devices. The method to determinate the threshold voltage in this thesis is the constant drain current method, the voltage at a specific normalized drain current NID is taken as the threshold voltage. This technique is adopted in most studies of TFTs. It can give a threshold voltage close to that obtained by the complex linear extrapolation method. Typically, the specific normalized current NID = ID/(W/L) is defined at 10nA for VD operated in linear region and 100nA for VD operated in saturation region, to extract the threshold voltage of TFTs in most papers.
The subthreshold swing S.S (V/dec) is a significant parameter to describe the control ability of gate bias toward drain current and the efficiency of the switch turning on and off.
It is defined as the amount of gate voltage required to increase/decrease drain current by one order of magnitude. It should be independent of drain voltage and gate voltage. However, in reality, the subthreshold swing might increase with drain voltage due to the short-channel effects such as charge sharing, avalanche multiplication, and punch through-like effects. It is also related to the gate voltage due to some undesirable factors such as serial resistance and interface state. In this experiment, the subthreshold swing is defined as one-second of the gate voltage required to decrease the threshold current by two orders of magnitude. The threshold current is specified to be the drain current when the gate voltage is equal to the threshold voltage.
The field-effect mobility (FE) is determined from the transconductance gm at low drain voltage (linear region). The transfer characteristics of poly-Si TFTs are similar to those of conventional MOSFETs, ignoring any other non-ideal effect and assuming the electric field in the channel is uniform, so the first order I-V relationship in the bulk Si MOSFETs can be applied to the poly-Si TFTs, which can be expressed as
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where Cox is the gate oxide capacitance per unit area W is channel width
Therefore, the field-effect mobility can be obtained by
gm
The mobility value was taken from Equation (2-4) with maximumFE.
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