1.1 Overview of Low Temperature Poly-Si Thin-Film Transistors
In recent years, the polycrystalline silicon thin-film transistors (poly-si TFTs) have been widely used in active matrix liquid crystal display (AMLCDs) [1.1]-[1.3] ,active matrix organic light emitting displays (AMOLEDs) [1.4]-[1.6]. Except large area displays, poly-Si TFTs also have been applied into some memory devices such as dynamic random access memories (DRAMs) [1.7], static random access memories (SRAMs) [1.8], electrical
programming read only memories (EPROM) [1.9], electrical erasable programming read only memories (EEPROMs) [1.10], linear image sensors [1.11], thermal printer heads [1.12], photo-detector amplifier [1.13], scanner [1.14], neutral networks [1.14]. The major attraction of applying polycrystalline silicon thin-film transistors (poly-Si TFTs) is in active matrix liquid crystal display (AMLCDs) lies in the greatly improved carrier mobility in poly-Si film and the capability of integrating the pixel switching elements and the capability to integrate sophisticated digital and analog driving circuit on the glass substrates[1.15]-[1.17]. For the poly-Si active layer, carrier mobility larger than 10 cm²/Vs can be easily achieved, that is enough to use as peripheral driving circuit including n-and p-channel devices (or p-channel only). Such performance brings the era of system-on-panel (SOP) technology. The process complexity can be greatly simplified to lower the cost (which save the IC and FPC BOM cost).
In addition, the mobility of poly-Si TFTs much better than that of amorphous ones, the dimension of the poly-Si TFTs can be made smaller compared to that of amorphous Si TFTs for high driving current and high resolution AMLCDs, and the aperture ratio in TFT array can be significantly improved by using poly-Si TFTs as pixel switching elements. This is because that device channel width can be scaled down while meeting the same pixel driving
requirements as in α-Si TFT AMLCDs.
The manufacture of polycrystalline silicon thin film transistors (poly-Si TFTs) embraces
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numerous steps commonly encountered in MOSFET fabrication for integrated circuits.
Despite the similarities, however, a number of key differences exist. These differences emerge primarily from the fact that the substrate of TFTs is no longer a single-crystal silicon wafer, but rather a heat-sensitive material such as glass. In MOSFET fabrication, poly-silicon is usually prepared by LPCVD and then annealed above 900C, namely, SPC (Solid Phase Crystallization) method. Unlike MOSFET devices, the TFT active layer needs to be formed on such amorphous host material and the temperature of all associated process has to be districted within the allowable range prescribed by the materials characteristics of the
substrate. For current display-glass substrates, maximum processing temperature needs to be kept below 650C. Even after considering possible exceptions to this maximum temperature such as RTA, the temperature range for fabrication on glass is severely constrained with respect to that on silicon. This limitation affects critical process steps, such as the gate-insulator formation and the activation of the doped regions of the device. These processes have to be reconsidered and optimized for TFT fabrication on glass. Hence, low temperature polysilicon (LTPS) technology is the novel technology specific for the flat panel display manufacture. Now, there are several ways to prepare the LTPS film on glass or plastic substrate: Metal-Induced Crystallization (MIC), Excimer Laser Crystallization (ELC), and Sequential Lateral Solidification (SLS), etc. Because of the methods mentioned above, the manufacturing technologies of poly-Si TFTs can lower the maximum process temperature enabling the use of low-quality glass and therefore reduce production cost [1.10].
Enhancing the performance of poly-Si thin-film transistors, as well as improve their reliability to realize various applications mentioned above. Recently, the performance gap between poly-Si TFTs and single-crystalline silicon devices has become smaller as a result of the advancement in poly-Si crystallization techniques. In comparing poly-silicon devices with their single-crystal counterparts, the major difference arises because of the presence of grain boundaries in the poly-Si. There are high density trap states in the grains and along the
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grain boundaries, and the electrical activity of the charge-trapping centers profoundly affects the electrical characteristics of poly-Si TFTs. Large amount of defects serving as trap states locate in the disordered grain boundary regions to degrade the ON current seriously [1.17]. In short, the grain boundary influences the TFT characteristics, and the typical
device characteristics of TFTs will be poor compared with the devices fabricated on single crystal silicon film.
Moreover, the relatively large leakage current is one of the most important issues of poly-Si TFTs under OFF-state operation [1.18], [1.19]. The dominant mechanism of the leakage current in poly-Si TFTs is field emission via grain boundary traps due to the high electric field near the drain junction [1.19]-[1.22]. Consequently, there are two ways to reduce leakage current: one is to reduce grain-boundary trap density and the other is to alleviate the electric field near the drain side.
To overcome this inherent disadvantage of poly-Si films, many researches have been focused on modifying or eliminating these grain boundary traps. Hydrogenation is a method for reducing the trap density in poly-Si films [1.23]-[1.25]. As the number of trapped carriers decreases, the potential barrier associated with the grain boundary also decreases.
The defect-state density can also reduced by improving the crystallinity of poly-Si film with techniques such as laser annealing [1.26]-[1.27] and solid-phase crystallization [1.28], [1.29]
to enlarge the grain size. For devices with smaller dimensions, the number of grain boundaries decreases since there are fewer grains within the channel region. Because the drain voltage drops on the depletion regions located at grain boundaries, a large electric field will exist in small dimension TFTs and make the drain current increase dramatically due to the impact ionization. Hence, a drain offset region or lightly-doped drain region is used to suppress leakage current by decreasing drain electric field.
The substrate dissimilarity, however, has an even more immediate impact on the process flow of TFTs. Unlike MOSFETs, Where the device active layer is part of the substrate, in the
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case of TFTs the active layer needs to be separately formed on the host substrate. The
common way of doing that, for poly-Si TFTs, is by deposition of an amorphous Si (a-Si) film on host substrate and the annealing step. Both of these steps affect the micro-structural quality of the result critically affected by the selection of techniques and operating parameters for the deposition and crystallization of the thin Si film. It should be further noted that these steps are also constrained, as far maximum temperature, per our earlier discussion.
1.2 Motivation
The market for liquid crystal displays has been rapidly expanding in recent years. The demand for a high luminance and a high contrast ratio in liquid crystal displays (LCDs), such as small-medium LCDs for projection device, mobile displays and displays for cars, is continuing to grow and seems insatiable. However, high luminance would increase photo leakage current (PLC) in the TFTs, which diminishes the voltages that are held across the pixel electrodes or affect the gray level controlling, which in turn, would cause a low contrast ratio and error color display. For instance, the off current of poly-Si TFTs exposure at the 3000nits backlight is higher than in the dark, which is about higher one order, shows as the Fig.1.1 and Fig.1.2. Not only low drain voltage but also high ones. It is suffer the On/Off ratio of device and will affect the TFTs operating. It goes without saying for the application of brightness about 8000nits in car. Consequently, it is necessary to suppress the PLC in LCDs with high luminosity.
Since the light emitted from back-light is mainly absorbed at the interface between the poly-Si layer and the buffer layer, plenty of electron-hole pairs are generated in the bottom of poly-Si film. It follows that the excess holes flow to the drain under the negative drain bias for p-channel devices, generating the photo leakage current. And the photo leak current depends linearly on the thickness of active layer while the electron-hole pairs are insensitive to the thickness [1.30]. Because the implant can increase trap density, the electron-hole pairs
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can recombine by the trap. To reduce photo leakage current IPLC, we designed poly-Si TFTs with different depth of implant and various dose of boron. As the key condition of photo leakage current are the bottom and thickness of active layer. We designed poly-Si TFTs with different thickness and two kind depth of implant. One is the poly-Si TFTs with two-thirds implanted depth of active layer and five thicknesses. Second is poly-Si TFTs with implanted the bottom of active layer and three thicknesses. In chapter 3, we canvassed our research in poly-Si TFTs with different active layer.
Low-temperature polysilicon thin film transistors (TFTs) employing excimer laser annealing (ELA) may be promising devices for high resolution active matrix liquid crystal display (AMLCD) owing to their high mobility and low thermal budget [1.31]. However, a critical problem of polysilicon TFTs is the kink effect caused by inherent floating body effect structure [1.32]. The TFT employing a counter-doped lateral body terminal is proposed to suppress the kink effect by collecting the counter-polarity carriers [1.33].
Because the TFTs with lateral body terminal (LBT) can collect the counter-polarity carriers, we designed TFTs with small LBT size and varied LBT position and varied channel length to make a study of the floating body effect and the photo characteristic of TFTs. In chapter 4, we canvassed our research in photo characteristics of Poly-Si TFT with counter-doped lateral body terminal.
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