2.1 Device Fabrication and Process Flow
In this section, we introduce the fabrication of the devices. The device structure is the conventional inverted-staggered back-gated TFT. First, we grew a thermal oxide layer of 5000 Å on the Si substrate. Then we deposited Al-Si-Cu of 3000 Å by using physical vapor deposition (PVD) as the gate electrode (Fig. 2.2 (a)). After defining the gate pattern, plasma enhanced chemical vapor deposition (PECVD) was used to deposit TEOS oxide as the gate insulator (Fig. 2.2 (b)). By using an RF sputter, an a-IGZO film was deposited as the channel layer (Fig. 2.2 (c)). A photoresist pattern was then generated with a standard lithographic process to define the source and drain regions (S/D) (Fig. 2.2 (d)). DC sputter was used to deposit a 3000 Å Al layer as the S/D electrodes by lift-off process (Fig. 2.2 (e)). The deposition power was fixed at 100 W and the working pressure was 1 mTorr with Ar flow rate fixed at 12 sccm (Table 2.2) (sccm denotes cubic centimeter per minute at STP). After the photoresist was spin coated on the device (Fig. 2.2 (f)) and exposed by DUV (Fig. 2.2 (g)), HCl:H2O=1:200 solution was used to define the active region (AA) (Fig. 2.2 (h)) . Finally, the gate contact region was opened by BOE:H2O=1:0 solution. After we scrapped the PR, the device was completed as shown in Fig. 2.2 (i).
The IGZO target we used was with the atomic ratio In:Ga:Zn:O=1:1:1:4. Here we have different channel deposition conditions with varying oxygen deposition rate. Devices with different channel thickness were also fabricated. The system’s working pressure was around 5 mTorr and the background Ar flow rate was fixed at 50 sccm. A change in the deposition power will change the deposition rate. In this study we choose rf power of 100 W as the
11
deposition condition of the IGZO film based on the experience revealed in reference [47].
Four different oxygen flow conditions, namely, 0, 1, 3, 5 sccm, corresponding to oxygen partial pressure of 0, 1X10-4, 3X10-4, 5X10-4 Torr, respectively, were used and the channel thickness was fixed at 15 nm for studying the effect of oxygen flow rate. The overall channel deposition conditions are summarized in Table 2.1. Effect of oxygen flow on the deposition rate is shown in (Fig. 2.1 (b)). Three different channel thicknesses, namely, 10, 15 and 20 nm, were targeted with fixed oxygen flow rate at 1 sccm for studying the effect of different channel thickness. TFTs with a channel composed of double active layers, which were deposited under different oxygen flow rate, as shown in (Fig. 2.2 (j)), were also fabricated and characterized. We defined the layer near the gate electrode as the 1st layer and the other one the 2nd layer. Four different oxygen flow conditions were used, namely, 1/3, 3/1, 1/5 and 5/1 sccm for the 1st/2nd channel layers, and the thickness of each layer is 7.5 nm in order to fix the total thickness at 15 nm. a-IGZO TFTs with gate dielectric thickness of 10 or 50 nm. The S/D metal deposition was done by either e-gun or sputter For studying the effect of the surrounding ambient, we expose the devices to atmosphere as long as 3 months, and compare them with the devices after 30 mins vacuum annealing. For the study of the effect of stressing and light, ±10 V gate voltage stressing and light exposure ranging 0 ~ 1000 s was applied on some of the devices. Finally, the temperature dependent effect was measured from 25 ℃ to 125 ℃.
12
2.2 Measurement Setup
In all of our study, the measurement of devices was executed by an HP4156A precision semiconductor parameter analyzer for Id-Vg and Id-Vd curves, and by an HP4284 precision LCR meter for CV curves.
Basic electrical parameters of the fabricated devices were extracted from the electrical characteristics. The threshold voltage (Vth) was extrapolated from Id-Vg curve which was defined as the gate voltage corresponding to a fixed drain current at 10-6 A under Vd of 0.1 V.
The subthreshold swing (SS) was calculated by the following equation
SS= ( ) , (Eq.2-1) where the minimum SS value was extracted in region when ID is between 10-9 A to
10-11 A. And the mobility (μ) was calculated by the following equation μFE= ‧ frequencies and obtained Rm and Cm in Fig. 2.3 (a) . Fig. 2.4 [21] is the measurement results of multi-frequency CV curves and the calculated results of Gm (inset) from Eq. 2.3 where Dm was the dissipation factor: Rs can be obtained at high frequency part in Zm versus frequency curve (inset of Fig. 2.5
13
[23]) and the Rs-vs.-voltage curve can be plotted as shown in Fig. 2.5 [23].
Furthermore, in order to obtain the density of states (DOS) of defects in the gap, should be calculated with the following procedure:
First, we calculate Z4 in Fig. 2.3 (b) with the following expression:
Z = Rs +
( ) − jw(
( ) + )， (Eq.2-5) where Rch and Cch are the channel resistance and channel capacitance, respectively. By comparing the real (A) and the imaginary (B) parts of impedance in Eq. 2.4 and Eq. 2.5, we can obtain Eq. 2.6 and Eq. 2.7 Then Rch are obtained with the following equations
= C R ， (Eq.2-8)
R = {1 + ( ) }B， (Eq.2-9) Then Cch can be calculated by using two frequencies from Eq. 2.10
C = Finally, we can calculate CLOC from the maximum value of
ω as shown in Fig. 2.6 [21]
with ωτ = 1. CFREE can be further obtained with the following relation:
C = C −
(ω ) ，
14
(Eq.2-13)
where CLOC and CFREE represent the capacitance components due to trapping/detrapping of localized electrons and free electrons, respectively (Fig. 2.3 (e) [21]). Here we simply define the energy level in the gap corresponding to the gate voltage at a specific current, say, 10-13 A, as “E1” and the surface band bending was calculated from the following equation
Φs= ∫ 1 −CCg
ox dV， (Eq.2-14) Finally, the DOS (denoted as g ) can be calculated from the following equation:
g (E) = ( )
× × × ， (Eq.2-15)
15