3.1 Device structure
The epitaxial layers of the metamorphic HEMT with InxAl1-xAs grading buffer layer were grown by molecular beam epitaxy (MBE). The cross-section of the MHEMT structure is shown in Fig. 3.1. The Indium graded InxAl1-xAs metamorphic buffer layer was grown on a 3-inch semi-insulating GaAs wafer, followed by an undoped In0.52Al0.48As buffer layer. 15 nm In0.52Ga0.48As was chosen as the channel layer. The Si-planar doping (2x1012 cm-2) layers were separated from the channel layer by 4 nm thin undoped In0.52Al0.48As spacer. The undoped In0.52Al0.48As Schottky layer was 15 nm. Then, the 18 nm thick In0.52Ga0.48As cap layer was highly doped with Si of 2x1018 cm-3 for Ohmic contact formation.
3.2 Ti/Pt/Cu Schottky diode sample preparation
The InGaAs/InAlAs samples used in this study were grown by MBE.
The structure of the samples consists of a 30 nm Si-doped n-InGaAs top of a 150 Å InAlAs Schottky layer on the GaAs substrate. The samples
by dipping in HCl: H20 (1:10) solution for 3 min. The samples were then immediately put into an electron-beam evaporating system and pumped down to a pressure of 8 × 10-7 Torr. Rectangular contact pads of Au/Ge/Ni/Au multilayer metals were evaporated on n-InGaAs and were RTA annealed at 320℃ for 20 s in nitrogen gas to form Ohmic contacts.
The Schottky contact materials, Ti/Pt/Cu were deposited by electron-beam evaporating system after InGaAs cap layer was etched.
Ti/Pt/Cu was also deposited on InAlAs wafer for material analysis. And different pretreatments were performed by HCl dipping, NH4OH dipping and N2 etching before Schottky metal deposition. The final thickness of these films was about 4000 Å. The diameter of the Schottky pattern was 1.23 mm. The current-voltage (I-V) characteristics of the as-deposited and annealed diodes were measured at room temperature using a HP4145B semiconductor parameter analyzer.
3.3 Device Fabrication
The fabrication process of the MHEMTs in this study includes:
1. Mesa/device isolation
2. Ohmic contact formation
Device isolation is the very first step of the whole HEMT fabrication process which was used to define the active region on the wafer. In these defined areas by lithography technique, the current flow is restricted to the desired path and each active device is isolated from each other (Fig 3.2). There are three typical ways to achieve device isolation: wet etching, ion bombardment, and selective implantation. Wet etching is the simplest way of the three. In this study Mesa isolation was carried out by a phosphoric based solution. The active areas were masked by Shipley S1818 photo resist. According to the device structure, the inactive era was etched to the buffer layer to provide good isolation. In order to avoid the photo resist peeling during the etching, the wafer surface was pre-treated before resist coating by Hexamethyldisilazane (HMDS). Finally, the etching depth was measured by α-step or surface profiler after the photo-resist was stripped and the etched profile was checked by Scanning electron microscopy (SEM). To inspect the mesa isolation process, a test pattern with a 10µm gap is used to measure the leakage current.
3.3.2 Ohmic contact Formation
After wafer cleaning by using ACE and IPA, the negative photo resist and I-line aligner were used to define the Ohmic pattern and make sure to form undercut profile for the metal lift-off (Fig 3.3). Ohmic metals multilayer Au/Ge/Ni/Au, from the bottom to the top, was deposited in the appropriate composition by e-gun evaporation system. After lift-off process, source and drain Ohmic contacts were formed after 320℃ for 20 sec in nitrogen atmosphere (Fig 3.4). Germanium atoms diffused into the InGaAs and heavily doped InGaAs during the thermal annealing process. The specific contact resistance was checked by the transmission line method (TLM) in the process control pattern monitor (PCM). The typical measured contact resistance was < 1 x 10-6 Ω-cm2 (Fig. 3.9).
3.3.3 T-shaped gate process
For high frequency and high speed application, short gate length with low gate resistance is expected. T-shaped gate structure was the most common approach for obtaining low gate resistance. According to the T-gate structure design, the gate length is defined by small footprint and the wide top offers low gate resistance.
T-shaped gates were achieved by using a multilayer resist technique with E-beam lithography. In this study, PMMA/copolymer was used as the resist system to form the T-shaped gates. The fabricated PHEMT in
this study has a gate length of 0.2µm.
Before T-gate lithography, in this study, Ohmic areas were exposed by optical lithography (Fig 3.5). Not only for gate metal, was Ti/Pt/Cu metal was also deposited on this area for Cu interconnect fabrication. Pt was effective diffusion barrier to keep Cu diffusion into the underlying Au layer.
After patterning the T-shaped gate, the exposed HEMT channel was recessed to achieve the desired channel current and pinch-off voltage characteristics. That means a groove is fabricated in the exposed surface of the wafer to “recess” the gate. This process is done by wet etch technique in this study, although dry etching methods may also be used.
The recess etching was conducted using PH-adjusted solution of succinic (S.A.) and H2O2 mixture to perform selective etching of the heavily doped InGaAs cap layer over InAlAs Schottky layer. The concentration of the etchant should be adjusted to provide an etch rate that is sufficiently slow to allow good control over the recess process, thus enable the operation to approach the target current value, without over etching it. The etching selectivity of InGaAs cap layer over InAlAs Schottky layer was beyond 100.The schematic of the HEMT with recessed gate is as shown in Figure 3.5, too.
The target current after the gate recess is a critical parameter affecting the HEMT performance. In order to get the desired recess depth,
method used to control the recess depth is to monitor the source-to-drain current during the etching process. For low noise PHEMT, the saturation current and the slope of the linear region go down as the recess groove was etched deeper and deeper. The wet etchant usually leaves a thin oxide on the InAlAs. HCl-based solution was used to remove the surface oxide.
After recess etching, Ti/Pt/Cu gate metal was evaporated and lifted off.
3.3.5 Device passivation and contact via formation
FETs are very susceptible to the surface condition, especially in the gate region. As the device scales down, the gate length and spaces of source-to-drain and gate-to-drain become smaller. In situation like this, the devices are very sensitive to the damages and contaminations such as chemicals, gases, and particles. The passivation layer protects the device from damage during process handling (such as “airbridge”) and wafer probing (Fig 3.7). The dielectric layer SiNx is a common choice for device passivation.
In this study, Samco PECVD system was used for depositing silicon nitride film. The processing gases of passivation PECVD were Silane, ammonia, and nitrogen. The process condition is: process pressure: 100Pa, process temperature: 300 °C and process time: 10 minutes to form the silicon nitride film 1000Å. The reflection index was inspected by Ellipsometer about 2.0.
Then the contact openings of the devices were formed by photo
lithography (Fig 3.8). The RIE was used to open the contact via hole region of the source and drain pads for interconnection. The plasma gases source for SiNx etching were mixture of CF4 and O2.
3.3.6 Airbridge formation
In order to reduce the total device area, finger-type layout was adopted. As a result, airbridge process was necessary to contact the fingers. The use of airbridge had several advantages including lowest dielectric constant of air, low parasitic capacitance, and the ability to carry substantial currents. The airbridge process flow will be discussed in detail in next section.
3.4 Airbridge formation
Airbridge is built by metal with air between the metal interconnect and the wafer surface beneath. Airbridges are used extensively in GaAs analog devices and MMICs for interconnections [3.1]. They may be used to interconnect sources of FETs, to cross over a lower level of metallization, or to connect the top plate of a MIM capacitor to adjacent metallization. The airbridges have several advantages including low parasitic capacitance, and the ability to carry substantial currents if the plated airbridge is thick enough.
Analog GaAs devices operating at high current density benefit from airbridges with thick plated metal layer. Low parasitic capacitance (between the bridge and any metallization beneath) follows from the large
spacing and low dielectric constant of the intervening medium. The capacitance is a function of the thickness, and the dielectric constant of the intervening material. Air (k=1.0) has a much lower dielectric constant than any other dielectric, and the space under the airbridge tends to be greater than the thickness of typical dielectrics. These considerations mean that airbridge crossovers are less capacitive than the dielectric type by a factor (typically) of five to twenty.
Traditionally, Au is used as the interconnect metal in III-V device fabrications, mainly owing to its high electrical conductivity and better chemical inertness with no surface oxidation. Recently Cu has been used widely in Si IC interconnects due to its low resistivity and high electromigration resistance. Both the resistivity and the material cost of Cu (1.67 µΩ-cm) are lower than those of Au (2.2 µΩ-cm). Based on the above advantages, Cu was used instead of Au as the airbridge metal in order to provide better thermal and electrical conductivities for the device applications.
3.4.1 Comparison between Au airbridge and Cu airbridge processes
The following process flow was used to fabricate the airbridge interconnects.
1. The first photolithography for plating vias 2. Thin metals deposition
3. The second photolithography for plating Areas.
4. Electroplating.
5. Second PR removal and thin metal etching.
6. First PR removal
7. Bridge Passivation. (For copper metallized airbridge only)
Table 3.1 shows the process flow of one conventional Au and two Cu-airbridge formation methods. There are three main differences between the fabrications of the Au airbridges and Cu airbridges: thin metal structure, electroplating and airbridge passivation.
Au airbridge used Ti/Au/Ti as thin metal while Ti/WNx/Ti/Cu was used in Ref [3.2] and Ti/Cu was used in this work for Cu airbridge.
Among the three airbridge processes, pre-plating etching was eliminated for the two Cu airbridge processes. Besides, compared to Au airbridge and Cu airbridge process in Ref [3.2], the selectively thin metal etching of the proposed Cu-airbridge process in this study was simplified as well.
For Au airbridge, Ti/Au/Ti metal system is chosen for thin metal. In Ref [3.2], Ti/WNx/Ti/Cu was their choice of thin metal. WNx was the diffusion barrier for Cu and the Au contacts (Ohmic and gate top metal).
In this study, the top metals of Ohmic and gate are both copper-based structure with diffusion barrier, so the thin metal structure was simplified to Ti/Cu without the worries of the diffusion between Au-based contacts and Cu interconnects. Moreover the Ti/Cu thin metal needed no additional layer of Ti to improve the adhesion in between seed metal and second photo resist. As for thin metal etching, the process was simplified as well because the simpler thin metal system. Finally the passivation of
The Cu airbridge process in this study will be expounded in detail in the next section.
3.4.2 The First Photolithography for Plating Vias
The thickness of the first layer of resist determines the spacing between the bridge and the material beneath (usually a dielectric). The thickness of the photo resist was about 2.5 µm. (Fig 3.10)
After the wafer was immersed in Acetone (ACE) and isopropyl alcohol (IPA) for 5 minutes, and dried by compressed dried air (CDA) blowing, the first layer of photo resist lithography was performed. The thickness was about 2.5 µm. In order to remove the thin PR residues in the exposed region, an O2 descum process was necessary after the photolithography. Then the wafer was plate-baked immediately after the ICP descum. This bake was used to evaporate the remaining solvent in the photo resist. On the other hand, the first photo resist must be sufficiently baked to prevent the “bubbling” after thin metal deposition and the later thermal bake of the second photolithography.
3.4.3 Thin Metal Deposition for Cu airbridges
The thin metal structure of the copper airbridge was Ti/Cu with Ti as the adhesion layers. The thicknesses of these two metal layers were 300 Å, and 1000 Å, respectively, from the bottom to the top. (Fig 3.11)
3.4.4 The Second Photolithography for Plating Areas
The second photolithography was performed on thin multilayer metals. The thickness of the second PR was about 2.5 µm. Same as the first lithography, descum is necessary to remove the polymer residues after development. (Fig 3.12)
3.4.5 Copper Electroplating
The wafer was cleaned before plating to prevent contamination. The wafer was dipped in the diluted sulfuric acid to remove the surface copper oxide. However, the sulfuric acid also attacks copper and the dipping time should not be too long. The wafer was dipped in the diluted sulfuric acid (1:10) for 5 seconds. The current density of the copper electroplating was 1 A/dm2 and the plating time was 10 minutes for 2.5 µm thick copper.
(Fig 3.13)
3.4.6 Plating PR. Removal and the Thin Metal Etching
The samples after electroplating were immersed in ACE to remove the second photo resist of the airbridges. (Fig 3.14) The thin metals used for the Cu airbridges were Ti/Cu. The wafer was dipped in the diluted sulfuric acid (1:10) for 5 seconds to remove the surface copper oxide. The thin copper metal was then etched by H2SO4/H2O2/H2O solution mixed in
the etching of copper stops at the underlying Ti as the color turned from red to grey.
Titanium was also etched by mixed 1:100 HF (49 %): H2O solution.
HF is the active ingredient in this etchant, so it also etches oxides.
Raising the fraction of HF in the solution increases the etching rate.
Titanium is readily oxidized, so it is likely to form an oxide layer from the water, which is readily etched by the HF in this solution, resulting in the formation of bubbles of oxygen. (Fig 3.15)
3.4.7 The First PR. (bottom layer) Removal
For copper airbridges, however, the PR residues were stripped by ultrasonic ACE bath instead of O2 plasma to prevent copper contamination of the ICP etcher.
For copper-metallized airbridges, the samples were dipped in ACE for 20 minutes to remove the first photo resist for plating vias. And then the specimens were dipped in IPA for 2 min. They were finally immersed in D.I. water, and then followed by CDA drying (Fig 3.16).
3.4.8 Airbridges Passivation
Silicon nitride was used as the passivation layer for copper airbridges to prevent surface oxidation. This dielectric passivation was deposited by plasma enhanced chemical vapor deposition (PECVD)
method. The SEM photograph of the copper airbridge with silicon nitride passivation is shown in Figure 3.17.
3.5 DC Characteristics
3.5.1 DC measurement
Keithley 2400 source meter, HP 4141B, and Karl Suss semi-automatic probe system was set up to measure the DC characteristics of the devices.
(1) I-V characteristics
In this experiment, the drain-to-source voltage was applied from 0 to 2 volts. The gate- to-source voltage range from 0 to -1.5 volts for low noise MHEMTs.
(2) Transconductance Gm
The drain-to-source voltage is biased at 1.5 volts and the gate-to-source voltage varies from 1.5 to -3 volts for GaAs low noise MHEMTs. The value of Gm was calculated by differentiating Id vs. Vgs
curve
3.5.2 Transmission line model (TLM) [3.3]
The resistance of the ideal planar contacts may be found using a transmission-line method (TLM). This technique is based on the assumption that specific contact resistance is determined by either the metal-semiconductor interface or by the interface between the alloyed and nonalloyed portions of the active layer, and the semiconductor resistivity under the contacts is uniform (through it may be different from that outside the contact). The typical TLM pattern used for the measurements is shown in Fig. 3.18 (a). The resistance between two adjacent pads of width W and length d separated by distance L is given by:
R=RsL/W+ 2Rc
Where Rs is the sheet resistance of the active layer between the contacts (i.e. the film resistance per square), Rs is the contact resistance.
The values of Rc and Rs were determined from the intercept and the slope of the R vs. L curve, as shown in Fig. 3.18 (b).
3.5.3 Breakdown characteristics [3.4]
Breakdown mechanisms and models are discussed in many articles.
One of them shows it is dominated by the thermionic field emission (TFE) / tunneling current in the Schottky gate contact area. Tunneling currents are known to increase with the temperature rising because the carriers
have higher energy to overcome the Schottky barrier which makes, according to this model, two-terminal breakdown voltage lower at higher temperature. Other model suggests the final two-terminal breakdown voltage is determined by impact-ionization determines, because the avalanche current decreases with increasing temperature. Lower avalanche current occurs at higher temperature because the phonon vibrations as well as carrier-carrier scattering increase with the increasing temperature.
As so far, breakdown mechanisms are still complicated to define clearly. Either model mentioned above is incomplete since coupling exists between TFE and impact ionization mechanisms. In addition, different devices may suffer from different breakdown mechanisms, depending on the details of the device design (insulator thickness, recess, channel composition, and so on). In this study, the gate-to-drain breakdown voltage is defined as the gate-to-drain voltage when the gate current is 1mA/mm.
3.6 RF Characteristics& Measurements 3.6.1 Scattering parameters [3.5]
Scattering parameters, generally referred to as S-parameters, are fundamental to microwave measurement. The scattering parameters are used to characterize the performance of a device. Figure 3.15 shows the two-ports 1 and 2.When the frequency is up to several GHz, the z-, y-, h- parameters can not be directly obtained by the open or short circuit
because of the reflected wave from the open or short terminations. The open or short terminations will induce the network oscillation. The relation of the microwave signals and s-parameters can be described as
S-parameters: ⎥⎦
a1: the electric field of the microwave signal entering the component input
b1: the electric field of the microwave signal leaving the component input a2: the electric field of the microwave signal entering the component output
b2: the electric field of the microwave signal leaving the component output
By the definition, then,
0
Therefore, S11 is the electric field leaving the input divided by the electric field entering the input, under the condition that no signal enters the output. The measurement includes instruments for the DC and RF measurement. Where a1and b1 are electric fields, their ratio is a reflection coefficient. Similarly, S21 is the electric field leaving the output divided by the electric field entering the input, when no signal enters the output.
Therefore, S21 is a transmission coefficient and is related to the insertion loss or the gain of the device. Similarly, S21 is a transmission coefficient related to the isolation of the device and specifies how much power leaks back through the device in the wrong direction. S22 is similar to S11, but looks in the other direction into the device. The s-parameters have both the amplitude and phase.
Therefore, S21 is a transmission coefficient and is related to the insertion loss or the gain of the device. Similarly, S21 is a transmission coefficient related to the isolation of the device and specifies how much power leaks back through the device in the wrong direction. S22 is similar to S11, but looks in the other direction into the device. The s-parameters have both the amplitude and phase.