27 start
Construct open segment candidates
Error output responses
Diagnosistic pattern
Pick one net candidate defect
Simulate physical information
Match output?
Collect True candidate Until injecting last open
segment candidates
True candidate open segment
defects Yes
No
end
Fig. 5.1 Diagnosis flow
After the diagnostic ATPG, the information about patterns and its matching outputs is available. Under the single defect assumption, we can diagnose the faulty circuit by a diagnosis flow shown in Fig. 5.1 and the proposed diagnosis flow can achieve high resolution.
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Fig. 5.2 Divide diagnosis flow into two stages
This flow mainly consists of two steps which are illustrated in Fig. 5.2: the first one is dictionary-based diagnosis and the second one is inject-and-evaluate diagnosis.
S1 S2
S3 S4
S5 G1
G2 G3 G4
Real defect occurs in S2 Fig. 5.3(a) defect occur in S2
Fig. 5.3(b) Pattern, P2 and its output result O2
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Fig. 5.3(c) Pattern, P3 and its output result O3
The diagnosis flow starts after deriving the diagnostic patterns for the circuit under test.
Correct logic values for all outputs can be obtained from the simulation. The first step is to construct open-segment candidates. We can get all faulty gate candidates by matching the real outputs and the patterns included in the diagnostic pattern information. Because the proposed ATPG targets the gate not the segment, we combine the faulty gate candidates to derive the corresponding faulty segments. This method can be viewed as one of the dictionary diagnosis approaches. Here shows an example. Fig. 5.3(a) shows a real defect that occurs on segment 2 (denoted as S2) driven by the gate G1. We apply all the patterns generated from our ATPG to testing and record the output responses. As S2 is open, two out of our diagnostic patterns will result in the error outputs and Fig. 5.3(b) and (c) show these two cases. Because the open S2 can affect gate G2 and gate G3 only, the pattern for G4 should not result in any error output shown as Fig. 5.3(d). With our diagnostic patterns and matching information, we can compose the defect location in Fig. 5.3(e).
Fig. 5.3(d) Pattern, P4 and its results
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S1 S2
S3
S4
S5
G1
G2
G3
G4 Using the faulty gates information to
backtrace the defect
X
O X
Fig. 5.3(e) backtrace to the defect
Multiple open-segment candidates can be obtained from the first step. Next, we perform the silicon diagnosis in an inject-and-evaluate manner. During such second step, we choose one defect candidate at a time for injection and run simulation with the assistance of physical information. At the end, whether a candidate is a true or not depends on whether the simulation result matches the real silicon output result or not. If not, such defect candidate is eliminated. If yes, it remains in the defect pool as shown in Fig. 5.4 for silicon inspection in the future.
31 Real defect
Patterns Output results
Estimation defect
Patterns Output results
Estimation defect
Patterns Output results
Compare with output results
Match the estimate defect output and real defect output exactly
Fig. 5.4 inject-and-evaluate methods
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Chapter 6
Experimental Results
33 benchmark circuits, layouts and coupling capacitance information are available from TAMU websites [34]. The ISCAS 85 benchmark circuits are synthesized with a 5-metal-layer TSMC 180 nm CMOS technology. The threshold voltage of each type of gate is determined through SPICE simulation. For ATPG, we use a SAT solver named MiniSat 2.0 which is one of the best SAT solvers in practice. MiniSAT 2.0 is a fast complete SAT solvers and the source code is open for public.
Table 3 shows the gate-level and physical information of the ISCAS 85 circuit: the second row denotes the total number of nets; the third row denotes the number of nets with multiple fanouts; the forth denotes the total number of segments according to the layout of the circuits.
During the ATPG step, the testability of the circuit is incorporated in the-branch and-bound method. The original version of the-branch-and-bound method is proposed by Spinner [26], and always chooses logic-1 then logic-0 to justify (1->0). If the ATPG for justifying logic-1 fails, the algorithm will change to justify logic-0. Obviously, it is not necessarily better to start with logic-1. Therefore, three other different strategies are also proposed to guide the ATPG process: (1) 0->1: logic-0 is first justified and then logic-1; (2) controllability: the controllability values of the coupling nets for the target segment can determines the expected logic value of the target segment to be justified; (3) observability:
the observability value of the target segment determines the logic value to be justified.
Table 4 shows the runtime comparison of using the above 4 different strategies on some small ISCAS85 circuits. The first column shows the name of the circuits and column 2, 3, 4 and 5 shows the runtime in seconds for the 1->0, 0->1, observability and controllability strategies, respectively. As you can see, the 1->0 strategy is not necessarily superior.
Especially when the circuit size goes larger, the observability and controllability strategies both have better efficiency over the 1->0 strategy. Therefore, the observability strategy is
34
chosen to be incoportated in our ATPG algorithm.
Table 4 compare with other ATPG
circuit 1->0 0->1 observation controllability
c432 46 137 75 97
c499 497 542 507 470
c880 299 330 267 312
c1355 1124 993 873 884
After the ATPG process completes successfully, defects can be further classified into different categories, and Table 5 shows the statistics. The first column shows the number of ATPG-untestable defects which means that no pattern can be generated after trying the 2N or all possible combinations of the coupling nets for the target segment defect. The second column shows the number of aborted defects, which are defined as after trying up to five times the generated pattern cannot result in matching output responses with those from the physical simulation. The third and forth columns show the numbers of no-coupling defects and no-segment defects, respectively. Both categories are also classified as the structurally untestable. The last column shows the numbers for successful defects where a pattern can be successfully generated by the ATPG process.
Table 5 fault classification
circuit ATPG-
untestable aborted no-coupling no-segment successful
c432 15 4 28 7 292
After generating diagnostic patterns and collecting the pattern information, the diagnosis step proceeds and the experimental result is shown in Table 6. The first column represents the total runtime for diagnosis. Since the proposed diagnosis algorithm is dictionary-based, it runs efficiently. The second column represents the numbers of detected defects. In our experiments, 100 random defects are injected onto the circuit under test individually and 91 defects can be detected by our algorithm. The third column represents the number of candidate defects
35
reported by our diagnosis algorithm. For example, for c432, 91 defects are detected and only 91 candidate defects are reported, correspondingly. After checking the candidates against the injected defects, they are perfectly matched. The forth column represents the diagnosis resolution which is computed as the number of candidates divided by the number of injected defects. For example, the resolution is 1 for c432 and it means that our algorithm can find the exact defect on every defective circuit. The last column represents the total number of generated patterns. Note that we do not apply any compaction or compression technique on the pattern set and thus pattern reduction can be one of the future directions of this work.
Table 6: Diagnosis results
circuit Ddtime(s) detected candidate resolution # patterns
c432 11.584 91 91 1 292
c499 16.013 73 74 1.01 303
c880 41.526 83 84 1.01 615
c1355 145.753 70 70 1 729
c1908 91.917 68 68 1 1000
c2670 259.844 70 73 1.04 1801
c3540 445.219 79 79 1 2170
To fairly compare our diagnostic patterns and the diagnosis flow with other conventional random and 5-detect stuck-at patterns, in Fig 6.1 we also develop a dictionary-based diagnosis flow which consists of two parts: (1) the generation of the defect dictionary and (2) dictionary comparison.
36
Fig. 6.1 diagnosis flow for random patterns and 5-detection patterns
The first part of such flow applies the patterns set for simulation with the assistance of physical information against all possible defects. All the falling patterns and the related information including faulty driven gates, faulty segments and output syndromes are recorded to build a dictionary for diagnosis.
The second part of the flow is dictionary diagnosis. We first sample 100 same circuits with random injection of defects. After defect injection, we run the simulation with physical information. The third step validate whether the defect dictionary matches the output responses from the physical simulation on each pattern. If yes, the counts of defects are checked. Otherwise, we skip to the next pattern. If the count for one defect is equal to the expected value from the dictionary, such defect is saved as a true defect. Otherwise, it is removed.
Table 7 shows the information about the pattern sizes and their dictionary sizes for random patterns and 5-detect patterns. The total numbers of random patterns used in our experiments are 1000 while the 5-detect patterns are generated by a commercial tools with proper modifications.
37
Table 7: random patterns and 5-detection pattern fault dictionary
circuit # random
After applying the diagnosis flow, we can obtain the following two tables. Table 8 shows the diagnosis results for 5-detect patterns whereas Table 9 shows the results for random patterns. Column 1 shows the circuit name and column 2 shows the runtime required by the diagnosis process. Column 3 and 4 reports the numbers of defected defects and reported candidates whereas resolution in column 5 is computed by column 4 divided / column 3.
Column 5 shows the total number of patterns used for diagnosis.
38
Table 8: 5-detection patterns diagnosis result circuit Ddtime(s) # detected #
candidates resolution #patterns
c432 107.883 92 148 1.6 617
c499 613.446 77 262 3.4 794
c880 340.501 86 123 1.43 476
c1355 4093.384 80 232 2.9 1272
c1908 7565.367 75 240 3.2 1725
c2670 3126.143 75 182 2.43 786
c3540 6898.963 83 208 2.51 1465
Table 9: random pattern diagnosis results circuit Ddtime(s) # detected #
candidates resolution #patterns
c432 265.441 92 148 1.6 1000
c499 792.886 75 396 5.28 1000
c880 1260.463 85 125 1.47 1000
c1355 1480.233 80 291 5.74 1000
c1908 1942.933 70 419 5.99 1000
c2670 4624.633 64 267 4.17 1000
c3540 3070.196 70 392 5.6 1000
By comparing Table 8 and Table 9 with Table 6, we can observe that the proposed diagnosis with the diagnostic patterns run much faster than the dictionary-based diagnosis using random and/or 5-detect stuck-at patterns. Also, the result in Table 7 is worse than the other two on the numbers of detected defects. Besides the limitation due to the SAT solving in the ATPG process, there are two more limitations in the proposed flow: one is the success out of 2N trials in the-branch-and-bound search to derive a feasible coupling-net combination and the other is the success out of 5 trials in fault propagation of physical simulation to observe expected output responses. Both failures create extra un-diagnosable defects which are excluded from the defect dictionary. Comparing with the forth and the fifth columns in Table 7, apparently our diagnostic patterns with the proposed diagnostic flow can reach better resolutions for all benchmark circuits.
39
Chapter 7
Conclusion
40
When an open defect occurs on a segment of the circuit, physical characteristics of the circuit such as the layout and the cell library cause dynamic faulty behaviors under different input patterns. Such phenomenon is called Byzantine effect which makes open-segment defects not easy to be detected. Previous researches about open-segment defects mainly focus on ATPG and the diagnosis techniques and do not address the diagnosability of test patterns properly. The test set with high defect coverage does not necessarily accompany good diagnosability. Therefore, we are motivated to develop a two-stage algorithm including diagnostic ATPG and its diagnosis flow in the thesis.
The first stage for diagnostic ATPG aims to generate the patterns for all open-segment defects and consists of three steps: (1) finding a feasible coupling-net combination, (2) justifying a pattern conforming to the coupling-net combination, and (3) validating output responses through physical simulation. Branch-and-bound search, testability analysis and SAT solving techniques are integrated during this stage. Particularly, our indirect diagnostic ATPG targets each driven gate of the open segment instead of the segment itself, and greatly reduces the pattern size as well as the total runtime. In the second stage for diagnosis, defect candidates are composed according to information obtained during the previous stage in a dictionary fashion. As a result, only very few candidates are reported. Last, a inject-and-evaluate approach is applied to remove those candidates failing to match output responses against all patterns.
Experiments are conducted on ISCAS85 benchmark circuits and the result explains the effectiveness and efficiency of the proposed algorithm. For all ISCAS85 circuits, nearly 1 candidate that exactly matches the injected defect can be reported for each defective sample.
Due to the indirect diagnostic ATPG, the pattern size as well as the total runtime (including ATPG and diagnosis) is greatly reduced. The overall performance in terms of time is about 10X better than that from previous researches. However, some aborted defects may escape from our diagnostic ATPG pattern set and thus become our future work.
Other future directions include: (1) extending our algorithm to handle multiple defects, (2) applying pattern compaction and compression to further reduce pattern size, and (3) improving the timing performance by the replace of a better SAT solving engine.
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