In this section, we are going to discuss about the experiment result. Section 4.3.1 shows how much improvement of our TGs. We can find out that both TGs keep the speedup ratio while the core number increases. However, the simulation speed drops so quickly with core count. This is because the nature behavior of SystemC modeling. SystemC is an event-driven language. Since the behavior times increase, the simulation time also increase fast. The simulation speed of TG-1 and TG-2 getting closer when more cores need to simulate. This is because the transaction behavior on the system becomes more complicated. Memory and bus conflicts would be more when more master on a platform. Transaction behavior will need more percentage of simulation time than single core, especially for TG-2. However, we choose the AXI crossbar interconnect hierarchy in this experiment so the interconnect behavior simulation will not dominate full simulation time. The profiling result shows core’s
“inside” behavior, cache and file access, is more than half simulation time spends on TG-1 simulation. However, this result will change for different benchmark. In conclusion, TG-1 would take about half simulation effort for modeling cache behavior, TG-2 always pays almost 100 % effort on BIU. Obviously, TG-2 has simplified all cores’ internal behaviors.
Besides, the profiling results we show is under the default simulation which has only cycle count analysis. If we have turned on the analysis capability inside the TG model, the simulation speed and profiling result will changed and spend much effort on this functionality.
The off-line traffic generation shows ISS simulation would spend a long time.
Fortunately, we only need one time simulation for one source code. Since exploration would need repeat and repeat simulation, this simulation effort becomes not that important. TG-2 needs to re-simulate for different cache configuration. However, the simulation time is still
short. If design choices are few, the simulation time of cache model is acceptable. The functions below show total simulation time for our TGs and traditional ISS.
Total simulation time (ISS) = M х Full simulation time
Total simulation time (TG-1) = (ISS time + File translation time) +M х Full simulation time Total simulation time (TG-2) = (ISS time + N х (File translation time + Cache time))+ M х
Full simulation time
N is the number of total cache design choices need to explore, M is the times of full system simulation. Average overhead of off-line simulation will be smaller if there are more times of simulation on the full system. On the other hand, the traffic file size is also a serious problem. Traffic file of TG-1 might be amazing huge for large application. While more cores on a platform, TG-1’s traffic file will be a critical overhead for runtime simulation. In a conclusion, TG-1 is suit for large design space because no need to re-simulate. TG-2 is suit for smaller cache design space because it needs to re-simulate. Also, TG-2 is suit for big application benchmark because the smaller traffic size overhead.
5 C ONCLUSIONS
This thesis first address on the SoC design exploration issues and focus on simulation-based exploration methodology. We then target on a successful simulation framework, MPARM [20][21], and introduce how’s the environment set up by SystemC [15]
language. This case shows the full simulation environment is useful for designers to analyze performance of different hierarchy. However, the simulation speed is slow for modern multicore SoC design space exploration. This problem also exists while we rebuild a simulation environment in modern ESL tool [17]. The experiment shows it is still not enough fast. Many previous works focus on speedup simulation. Transaction Level Modeling [16][29]
does help exploration by arising modeling abstraction level but sacrificing simulation precision. TLM-based simulation helps to speedup interconnection behavior modeling but not improve processors’ inside computation behaviors. Traffic Generator could completely simplify processor’s computation modeling. Nevertheless, TG-based simulation usually is not the real case, or TG directly replays last time’s simulation. These two methods both have their
We proposed a TG-based exploration acceleration approach to deal with those problems.
Our TGs combine both TLM’s and traditional TGs’ properties in our framework. Our TGs support multiple on-chip bus protocols, multi abstraction level and cache behavior simulation.
Most of important, our TGs’ transaction behavior is based on real application not the statistical traffic result. Also, our TGs no need to simulate full system for recording traffic.
The propose simulation flow is separated into two phases: off-line traffic generation and ESL simulation. TG-1 solution off-line simulates cores’ ISS behavior and keep cache modeling contain in ESL simulation environment. TG-2 solution off-line simulates cores’ ISS and caches’ behavior and completely simplifies TGs’ modeling in ESL simulation environment.
We supply a tool chain for full simulation framework and set up a traffic format to be used for both TG solutions.
We further verify our TGs’ accuracy compared to the ARM ISS model. Our TGs have at least 90% accuracy compared to ARM ISS model. Then we build up an experiment for measuring simulation speed. Experiment shows our proposed TGs do speedup simulation, TG-1 is about 4 times improvement over ARM ISS, and TG-2 is about 6 times. This proves that our exploration framework could be used for SoC design which has already decided target processor. The simulation profiling shows TG-1 is suit for large design space especially focuses on cache organization and interconnection network co-exploration. TG-2 is suit for design space focuses on interconnection network exploration with fewer cache deign choices.
Our future work is to enhance the modeling capabilities including semaphore interface between TGs to support multicore issues. Cache models for multi-processor data coherent problems and multi-level cache hierarchy supporting. Moreover, the simulation speed could be improved by traffic file compression techniques to lower system overhead.
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作者簡歷
顏于凱，1984 年 6 月 30 日出生於高雄縣。2006 年取得國立交通大學電子工程學系
學士學位，並繼續在國立交通大學電子工程研究所攻讀碩士。2008 年在劉志尉教授指導
下，取得碩士學位。本篇論文「嵌入式系統晶片之匯流排與記憶體設計探索」為其碩士 論文。