Chapter 1 Introduction
1.3 Dissertation Organization
In this section a brief outline of this dissertation will be given as following. Chapter 1 gives a brief introduction which introduces active device in different aspect and study motivation.
Chapter 2 presents an annular-type layout structure of RF LDMOS. The DC, high-frequency
and RF power performance were analyzed and compared to traditional structure. This chapter
also presents the unusual behavior in capacitance of RF LDMOS with square and annular
structures. Chapter 3 describes the theory of polyharmonic distortion model and show the
measurement and simulation results of RF LDMOS transistor in annular structure. Chapter 4
presents the sensor circuit design using active device and SAW device. The fabrication of
SAW devices and the related oscillating circuit using active device in CMOS process are
investigated in this study. The final chapter summarizes this study.
Fig. 1.1 A cross section of traditional high-power LDMOS transistor.
Chapter 2
Characterization of Annular-structure RF LDMOS
2.1 Introduction
Silicon laterally diffused metal oxide semiconductor (LDMOS) transistors have been of
great interest due to their applications in RF amplifiers in wireless communication systems or
base-stations [24]. LDMOS transistors provide several advantages, including high efficiency,
low cost and good linearity capability on silicon substrates. Scaling down the gate length or
the drift length of LDMOS transistors improves their performance by producing lower
on-resistance and higher transconductance. However these scaling approaches may limit
high-voltage endurance during power-amplifying operations.
In addition to scaling down the device or changing device processes, researchers have
studied several transistor layout styles in their search for the best device performance [25].
These designs must deal with the tradeoff between layout area and reduced parasitic. The
results presented in this study show that closed transistors offer many promising
characteristics. The most widely used closed topology is the square-structure transistor as
shown in Fig. 2.1. The square-structure transistor has lower on-resistance and higher
transconductance, as described in [26]. However, square-structure corners contribute very
applied voltage is high with respect to the channel length, the electric field in the corners
could break the device. In this case, a circle-type layout, called an annular structure in this
paper, would be the optimum layout type for ensuring the most uniform current flow.
However, some works are only published in a square shape or polygonal shape due to foundry
process restrictions [28][29]. Besides, this study also performs the capacitance analysis. Due
to the capacitance influence of the input and output of enclosed devices, which are significant
in dynamic operation and have an impact on device high-frequency performance, many
studies have been published on the capacitance characterization and modeling of LDMOS
transistors [30-32].
2.2 Annular-structure RF LDMOS
2.2.1 Device Design and Fabrication
In this study, fabricates the annular-structure RF LDMOS transistors were fabricated using
a 0.5 μm LDMOS process. The standard LDMOS layout consists of a source and a drain
separated by a channel of width W and length L. An annular-structure LDMOS consists of a
transistor with the source diffusion in the middle, encircled by the gate channel and the drain
diffusion to achieve a lower ON-resistance [33]. The channel width for annular structure is
the length of the curve lying at mid-channel.
Figures 2.2 and 2.3 show the die photo and single cell layout of an annular-structure LDMOS
transistor. Figure 2.4 illustrates the schematic cross section of this device. The gate oxide
thickness was 135 Å and the mask channel length (LCH,shown in Fig. 1.1) was 0.5 μm. The
drift length (LDrift=LOV+LFOX) was 2.4 μm. The drain region was extended under the field
oxide (FOX), consisting of a lightly doped N-well drift region and an N region with higher
doses for on-resistance control. This design ties the source region and the p-body together to
eliminate extra surface bond wires, reduce the source inductance, and improve the RF
performance in a power amplifier [34]. This study optimizes the LDMOS transistor layout for
high-frequency performance with a GSG structure adapted for on-wafer measurement.
2.2.2 DC Characteristics
Generally speaking, the DC characteristics of LDMOS are similar to the MOSFET.
Nevertheless, at high drain voltages, the MOSFET suffers a breakdown caused by the high
voltage across the oxide at the drain end of the gate, resulting in high gate-drain current flow.
Another effect arising from the high electric field in this region is hot-carrier injection.
However, in the LDMOS structures, these high-field effects are mitigated. The use of a
lightly-doped n-type region at the drain end of the gate moves the heavily-doped drain contact
region away from the high field region, and has a number of benefits. The lightly-doped
semiconductor can support a high voltage, enabling the high RF voltage swing required for a
high-power device. The electric field in saturation at the drain edge of the gate is reduced,
thereby reducing the hot-carrier injection and increasing the gate breakdown voltage [35].
The LDMOS transistor with larger LDrift revealed a lower drain current and
transconductance. Moreover, the breakdown voltage was higher with a larger LDrift device.
For a larger LDrift, the higher resistance in the drift region results in a large voltage drop which
increased the carrier velocity and go into the velocity saturation easily. The velocity saturation
in the drift region is called “quasi-saturation” while intrinsic MOS is still in linear operation.
This effect is generally observed at high gate voltages. When the device go into the
quasi-saturation, the gate control ability decreases which limits the drain current level and
delays the transition between linear and saturation region [36].
2.2.3 High-frequency Characteristics
Through small-signal equivalent circuit analysis of a MOSFET, we can realize the effect of device parameters on high-frequency characteristics easily. We adopted a simple equivalent
circuit of the LDMOS by the method described in [37]. The equivalent circuit is shown in Fig.
2.5. After de-embedding the extrinsic parasitic resistances and the substrate-related
parameters, the intrinsic components can be directly extracted from intrinsic Y-parameters by
the following equations [38]:
)
which is related to the intrinsic transconductance (gm) and input intrinsic capacitances (Cin =
Cgs + Cgd). The approximate maximum oscillation frequency (fmax) can be expressed as
follows [39]:
) (
8
max
f
T4 g
DSR
gf
TC
gdR
gR
df ≈ + π + α
(2.9)The drain-to-substrate junction capacitance (Cjdb) refers to the deep n-well (DNW) to
p-usbstrate/p-body junction capacitance and this capacitance also has impact on fmax.
2.3 Annular-structure and Square-structure Comparison
2.3.1 Effective Transconductance Evaluation
The initial problem in an annular-structure LDMOS is the definition of the aspect ratio W/L,
which is not as complicated as in standard devices. However, defining the width (W) of the
annular structure is less straightforward. For example, the width (W) can either the length of
the curve lying at mid-channel, or the drain/source diffusion perimeter.
This study extracts the experimental W/L values by comparing the ID-VGS characteristics of
an annular-structure transistor and a standard transistor with the same L. The SPICE model
can be used to extract W/L from the ratio of transconductances gm as follows [40]:
( ) (1 )
where the superscripts ‘std’ and ‘closed’ refer to the standard geometries and closed structure
(square/annular structure), respectively. As the effective aspect ratio of the standard transistor
that was called fishbone structure was known, the aspect ratio of the square/annular structure
can be determined.
Figure 2.6 shows the I-V characteristics of a LDMOS under static conditions. The DC
characterization of the DUT was performed using an Agilent semiconductor parameter
(4156C) analyzer. In saturation region, the annular structure shows a higher drain current and
transconductance than the square structure. These are attributable to the larger equivalent W/L
and smaller drain parasitic resistance. The effective annular structure width is 83.2 μm
compared with fishbone structure (W = 80 μm). These results show that the annular structure
has better DC performance than the square structure.
2.3.2 Capacitance versus VGS and VDS
This section extracts the gate-to-source/body capacitance (CGS + CGB) and gate-to-drain
(CGD) capacitance from the de-embedded S-parameters in the low-frequency range [41]. The
other capacitance extraction method was performed in the Appendix 1. Figures 2.7 and 2.8
show the extracted CGS + CGB and CGD of RF square-structure and annular-structure LDMOS
transistors at room temperature. At VDS = 1 V, both square and annular structures have similar
curve traces because they share the same physical mechanism. In terms of the lateral
non-uniform doped channel in LDMOS, the drain end will be inverted prior to the source end,
resulting in a peak in CGD. As the drain voltage VDS exceeds 5 V, the CGS + CGB and CGD all
start to reveal distinct peaks. This is because the inversion charges are injected to the depleted
area of the drift. Therefore, the CGD and CGS + CGB increase with increasing VG, and the CGS +
CGB increases suddenly over the flat of the inversion area to reach the maximum at the onset
of quasi-saturation [36]. The reason for this phenomenon is that a higher VD leads to a higher
VG at the onset of quasi-saturation, and so the peaks shift to a higher VG.
However, for the square structure, Fig. 2.7 shows a second peak in CGS + CGB and CGD at
VDS = 10 V. Figure 2.9 shows a uniform current distribution across the region from drain to
source in annular structures. Because the corners of the drift of square structure show a lower
current density than the edges, square-structure device must provide higher gate voltage to go
into quasi-saturation. In other words, besides the first peak results from the edges of the
square structure which went into the quasi-saturation region in advance, the second peak
appears when the corners start to go into quasi-saturation at VG is approximately 6.5 V when
VDS = 10 V.
2.3.3 High-frequency Characteristics and Power Performance
To characterize the high-frequency performance and determine the maximum cutoff
frequency (fT) and maximum oscillation frequency (fmax) of annular-structure LDMOS
transistor, this study measures S-parameters on-wafer from 0.1 to 20 GHz using an Agilent
performance network analyzer (E8361C) and then de-embeds them using the OPEN dummy
[42]. The cutoff frequency and maximum oscillation frequency are the frequency where the
current gain was 0 dB and the frequency where MSG was 0 dB, respectively. The
measurement results of fT and fmax for annular-structure LDMOS are shown in Fig. 2.10. At
VG = 2 V and VD = 20 V, the cutoff frequency and maximum oscillation frequency are
approximately 5 GHz and 12 GHz, respectively.
This study measured power performance using a load-pull system consisting of HP85122A
and ATN LP1 at the cascade probe station, with the probe calibrated using a standard
calibration substrate. Figure 2.11 shows the transducer power gain and efficiency of different
layout structures. In the case of the load-pull measurement, the operating frequency was 1.9
GHz and the source and load impedances were biased at VD = 20 V and VG = 2.5 V, which
are maximum cutoff frequency values. Figure 2.11 indicates a power gain of over 12 dB and
an input power 7 dBm at the 1-dB compression point. The power added efficiency (PAE) at
this point is over 20%. Figure 2.11 also shows that the annular structure had higher power
gain and efficiency than the square structure. This result might be attributed to the larger
equivalent transconductance of the annular structure.
2.4 Summary
Two types of layout structures of RF LDMOS transistors for DC, capacitance and power
characteristics were investigated. The annular-structure LDMOS transistor had a better
performance than the square structure without changing the process flow. The higher drain
current in the annular structure LDMOS was due to less corner effect compared with square
structure. According to the capacitance extraction results and power performances, the
annular structure is superior to the square structure in layout type of LDMOS transistor.
(a)
(b)
Fig. 2.1 The traditional LDMOS layout structure: (a) fishbone and (b) square.
Fig. 2.2 The die photo of annular-structure RF LDMOS.
Fig. 2.3 The cell layout of the annular-structure RF LDMOS.
Fig. 2.4 Schematic cross section of the LDMOS transistor.
Fig. 2.5 A simple equivalent circuit model of the LDMOS.
0 5 10 15 20 25 30
Fig. 2.6 (a) Output and (b) subthreshold characteristics of LDMOS transistors for different
-4 -2 0 2 4 6 8 0.1
0.2 0.3 0.4
2nd peak at VD=10V
VD=1V VD=5V VD=10V VD=20V
Gate Voltage (V) C
GS+C
GB(pF)
1st peak at VD=10V
50 100 150 200 250
C
GD(f F)
Fig. 2.7 Extracted CGS+CGB and CGD versus gate voltage with different drain biases for
square-structure LDMOS transistor.
-4 -2 0 2 4 6 8 0.1
0.2 0.3 0.4 0.5
VD=1V VD=5V VD=10V VD=20V
Gate Voltage (V) C
GS+C
GB(pF)
50 100 150 200 250
C
GD(fF)
Fig. 2.8 Extracted CGS+CGB and CGD versus gate voltage with different drain biases for
annular-structure LDMOS transistor.
(a)
(b)
Fig. 2.9 Schematic view of layout structure and current distribution in RF LDMOS. (a) square
structure and (b) annular structure.
1E8 1E9 1E10 1E11
Fig. 2.10 Cutoff frequency (fT) and maximum oscillation frequency (fmax) of annular-structure
LDMOS at VD = 20V, and VG = 1, 2, 3 V
-20 -15 -10 -5 0 5 10 -10
-5 0 5 10 15 20
Annular-structure Square-structure
Pin (dBm)
Ga in (d B ), Po u t (d B m )
0 5 10 15 20
PAE (%)
Fig. 2.11 Output power and efficiency versus input power at 1.9 GHz, VD = 20V, and VG =
2.5 V with different layout structure.
Chapter 3
RF Transistor PHD Modeling
3.1 Introduction
Modern communication systems are nowadays complex to permit complete simulation of
the nonlinear behavior at the active device level. In addition to small-signal and parasitic
analysis for active devices, linearity and power analysis are the most important factors in RF
amplifiers because it leads to intermodulation distortion. This type of distortion creates
undesired signals, similar to the operation signal, in the amplifier input. In particular, the third
order intermodulation distortion (IMD3) must be minimized because it generates harmonics
that interfere with the desired signal. As a result, many studies have been dedicated to
developing large-signal models to predict the nonlinear behavior of active devices [43-46].
Though these nonlinear models can predict the large signal operation of active devices
accurately using suitable equivalent circuits or mathematical equations, they may be
unsuccessful in other kinds of active devices or foundry processes. Optimizing circuit
performance and reducing product time to market for accurate large-signal models remains an
essential.
An alternate way to construct a large-signal model is to use the measurement-based
behavioral method proposed by [47], called the polyharmonic distortion (PHD) model. This
model is based on X-parameters, which are extensions of S-parameters with nonlinear
components measured using a nonlinear vector network analyzer (NVNA) [48]. S-parameters
are perhaps the most successful parameter ever. These parameters have the powerful property
that the S-parameters of individual components are sufficient to determine the S-parameters
of any combination of those components [49]. S-parameters are sufficient to predict its
response to any signal, provided only that the signal is small amplitude or power. Despite the
great success of S-parameters, they have several limitations. The S-parameters are defined
only for linear systems, passive component, or systems behaving linearly with respect to a
small signal applied around a static operating point at active device. In fact, all systems are
nonlinear in real world. Sometimes, they generate harmonics and intermodulation distortion.
Therefore, the S-parameter analysis technique doesn’t apply to such systems. X-parameters
include harmonic tone and intermodulation frequency component, and also the relationships
between all those frequencies for given amplitude and frequency; therefore the X-parameters
enable the engineer or system designer to acquire the complete spectrum or waveforms of
nonlinear system [48]. Unlike S-parameters, the engineer could obtain the linear device
behavior and nonlinear behavior about a large signal operation point from the X-parameters.
As discussed in a study [50], this measurement-based large-signal model facilitates
amplifier design with RF simulation tool. Moreover, this study succeeds in calibrating the
NVNA reference plane to probe tip. This study also presents the nonlinear behavior of RF
LDMOS transistors using the PHD model because the NVNA must calibrate the comb
generator and power meter before large signal measurements.
3.2 Polyharmonic Distortion Model Theory
The waves of S-parameter are defined as linear combinations of the signal port voltage, V,
and the signal port current, I, whereby the current quantity is defined as positive when
traveling into the DUT. The incident and scattered wave are called the A-wave and the
B-waves, respectively [49]. They are defined as follows:
2
The value of the characteristic impedance Z0 is 50 Ω. This analysis aimed at PHD model will
be working with nonlinear functional relationships between the wave quantities. This derived
process of PHD model is very different from S-parameters that can only describe a linear
relationship. The PHD model assumes that the discrete tone signals appeared on the incident
as well as for the scattered waves. Furthermore, these discrete tones may appear at arbitrary
frequency, as explained in [48]. For a given active device, determine the set of complex
functions Fpm(.) that correlate all of the relevant input components Aqn with the output
components Bpm, where q and p are from one to the number of signal ports, and m and n are
from zero to the highest harmonic index. The mathematical equation expressed as
,...)
Note that the complex functions Fpm(.) are called the describing functions [51]. This
mathematical equation is illustrated in Fig. 3.1. The spectral mapping (3.3) is a very general
mathematical form; therefore the practical models can be developed in the frequency domain
from this form. The PHD model is a special approximation of (3.3), which involves the
linearization of (3.3) around the incident or scattered signal.
A first property is that Fpm(.) describes a time-invariant system. This implies that applying
an arbitrary delay to the input signals, the incident A-wave, always results in exactly the same
time delay for the output signals, the scattered B-waves. In the frequency domain, applying a
time delay is equivalent to add a linear phase shift (θ). Therefore, the complex function
equation (3.3) can be expressed as
,...)
In the following, both of the properties discussed previously are exploited to derive the PHD
model equations. Because the (3.4) is valid for all values of θ, we can make equal to the
inverted phase of A11 which is the incident fundamental. The choice is not unnatural for
power transistor and power amplifier applications, since A11 is the dominant large-signal
input component.
For expression elegance, the phasor P is introduced and is defined as
) (A11
e j
P= + ϕ (3.5)
Substituting ejθ by P-1 in (3.4) results in
m pm
pm F A A P A P A P A P P
B = ( 11, 12 −2, 13 −3,...,× 21 −1, 22 −2,...) + (3.6)
The benefit of (3.6), compared to (3.3), is that the first input argument will always be a
positive real number, that is to say, the amplitude of the fundamental component at the input
port 1, instead a complex number.
The harmonic superposition principle is illustrated in Fig. 3.2. To keep the diagram simple
and elegance, this PHD model derived thereafter only consider the presence of the A1m and
B2n components and neglect the presence of the A2m and B2n components. The harmonic
superposition principle is important concept to the PHD model. Linearization of (3.6) versus
all components in this equation besides the large signal A11 results in
Note that the real and imaginary parts of the input arguments are considered as separate and
independent parts. The PHD model equation is derived by substituting the real and imaginary
parts of the input arguments in (3.7) by a linear combination of the input arguments and their
corresponding conjugates. Since
2
The (3.7) can be rewritten
⎟⎟
Rearranging (3.10), and then the simple PHD model equation as follows
)
According to aforementioned PHD model deduction, to analyze the nonlinear behavior of
optimization, the PHD model is a good way to analyze the nonlinear characteristics for active
devices. The X-parameter in Agilent nonlinear vector network analyzer expression is given by
(3.16).
Here the scattered and transmitted waves, BPK, at port P at the Kth harmonic frequency,
divided into three terms. The first term represents the large-signal response of the device to a
single large-amplitude tone (A11) at a given fundamental frequency, assuming match all ports
at all harmonic frequencies. The second and third terms depict a linear non-analytic mapping
of incident phasors at port Q and harmonic frequency index L into complex output phasors at
port index P and harmonic frequency index K. The term G is the phase of the input large tone.
The sum of this equation includes all ports and indicates the number of harmonics measured.
The sum of this equation includes all ports and indicates the number of harmonics measured.