In chapter 1, some backgrounds about LTPS TFT is introduced in this section : overview of poly-Si TFTs; LTPS TFTs with high-k gate dielectric; overview of metal-induced lateral crystallization; negative bias temperature instability in LTPS TFTs; and reliability issue on high-κ gate dielectric.
In chapter 2, we describe the device fabrication and the methods to extract the typical characteristic parameters of LTPS-TFTs in our experiment.
In chapter 3, electrical characteristics of high performance SPC and MILC p-channel LTPS-TFT with HfO2 gate dielectric are characterized, for comparison.
In chapter 4, the NBTI degradation mechanism in LTPS TFTs with HfO2 gate dielectric has been investigated with a conventional DC measurement technique.
Besides, the reliability comparisons for SPC and MILC devices have been studied systematically.
In chapter 5, the drain bias effect on negative bias temperature instability (NBTI) degradation mechanism in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) with high-k gate stack is analyzed by the DC measurement technique. In addition, the NBTI model with drain bias effect is established.
Finally, we conclude all experiments results briefly in chapter 6.
14
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24
(a) Before annealing
(b) After annealing and MIC region formed
(c) After annealing and MILC region formed
Fig. 1. MILC polysilicon formation during annealing process.
25
Fig. 2. MILC polysilicon formation mechanism.
26
Chapter 2
Device Fabrication and Method of Parameter Extraction
In this thesis, high performance p-channel low temperature poly-silicon thin-film transistors (LTPS-TFTs) are fabricated by the employment of HfO2 gate dielectric and two crystallization methods, solid phase crystallization (SPC) and metal-induced laterally crystallization (MILC), for comparison. In addition, we will introduce the methods to extract the typical characteristic parameters of LTPS-TFTs, such as threshold voltage VTH, subthreshold swing S.S., drain current ON/OFF ratio, field effect mobility µEF, and the trap state density Ntrap. All the electrical characteristics were measured by Keithley 4200-SCS.
2.1 Device Fabrication
As shown in Fig.1 and Fig.2, the fabrication of devices started by depositing a 50-nm undoped amorphous Si (α-Si) layer at 550°C and 120m torr in a low-pressure chemical vapor deposition system on Si wafers capped with a 500-nm thermal oxide layer. For SPC LTPS-TFT, the 50-nm α-Si layer was crystallized by SPC process at 600°C for 24-h in a N2 ambient. For MILC LTPS-TFT, a 5-nm Ni was deposited by electron-beam evaporation system at room temperature, 10-6 torr base pressure and 10-5 torr process pressure, and patterned by lift-off process as a seed layer to crystallize the α-Si. Then the 50-nm α-Si layer was crystallized by MILC process at 550°C for 24-h in a N2 ambient, and the residual Ni was removed by H2SO4 + H2O2
solution. Here, both SPC and MILC poly-silicon channel films have been formed.
Then a 500-nm plasma-enhanced chemical vapor deposition (PECVD) oxide was deposited at 300°C for device isolation. The device active region was formed by patterning and etching the isolation oxide. The source and drain regions (S/D) in the
27
active device region was implanted with boron (10 keV at 5 x 1015 cm-2). The S/D was activated at 600°C for 24-h annealing in a N2 ambient. A 50-nm HfO2 was deposited by electron-beam evaporation system at room temperature, 10-6 torr base pressure and 10-5 torr process pressure. An O2 annealing in furnace was applied to improve the HfO2 at 400°C for 30-min. In order to compare the HfO2 gate dielectric, a 50-nm PECVD SiO2 was also deposited at 300°C in SPC poly-silicon channel film. After the patterning of S/D contact holes, aluminum was deposited by thermal evaporation system at room temperature, 10-6 torr base pressure and 10-5 torr process pressure, as the gate electrode and S/D contact pad. Finally, the TFT devices were completed by the contact pad definition. All process flow is shown in Fig. 1 and Fig.2 . Devices with gate width (W) and length (L) of 10µm /10µm are measured.
2.2 Method of Parameter Extraction
2.2.1 Determination of Threshold Voltage
Threshold voltage VTH is an important parameter of semiconductor devices.
However, various definitions for VTH have been proposed on different types of device.
In MOSFET, there are two common methods for determination of VTH. One is the linear extrapolation method, which is defined in “linear-scale” ID-VGS curves at a low drain voltage (50~100mV). According to ideal ID vs. VGS equation
(1)
(2) We have to note that equation (2.2) is accurate only for negligible series resistance like source and drain resistance RSD, which can be generally negligible at the low drain current (or low drain voltage). VTH is defined from the extrapolation of
28
Gm,max, which is common practice to find the point of maximum slope of the IDS-VGS curve ( !) and fit a straight line to extrapolate at ID=0. The real ID-VGS curve deviates from a straight line at gate voltage below VTH due to subthreshold current, and above VTH due to series resistance and mobility degradation effect. Hence the VTH is determined from the extrapolated intercept of gate voltage (VGS) at ID=0 by
"#$ (3) In our thesis, VTH is defined differ from above description and is defined by more simply way which called constant drain current method. This method can be found in almost the papers relate to poly-Si TFTs. The VTH obtained from this way is close to the another extracted from linear extrapolation method. Here, constant drain current is fixed to when I = (W/L)*100 nA for p-channel at VDS=|0.1|V and W, L are channel width and length respectively. In this thesis, devices were all measured by W=10 µm, L=10 µm. Thus, Ids was fixed to 10-7 A in all our discussion.
2.2.2 Determination of Subthreshold Swing
Subthreshold slope (S.S.) is a typical parameter to describe the control ability of gate toward channel, which reflects the turn on/off speed of a device. It is defined as the amount of gate voltage required to increase/decrease drain current by one order of magnitude.
The S.S. should be independent of drain voltage and gate voltage. In reality, however, the S.S. increases with drain voltage due to channel shortening effect such as charge sharing, avalanche multiplication and punchthrough effect. The subthreshold slope is also related to gate voltage due to undesirable and inevitable factors such as the serial resistance and interface states. In LTPS-TFTs, the
29
subthreshold swing is also dependent on defects and grain boundaries in ploy-Si channel films. It has been reported that S.S. be closely related to the trap states located near the mid-gap (deep states), which originate from dangling bonds [2.1]. Besides, because of the limitation of low temperature process, the poor interface between the gate dielectric and silicon substrate has been observed. Both bulk and interface traps would make poor S.S. in LTPS-TFTs. The formula of subthreshold slope were defined as
%& %& '()*+,("-$#$ ./ (4) In our thesis, the S.S. is defined as one-half of the gate voltage required to decrease the threshold current by two orders of magnitude. In some of stress conditions, the S.S. is defined as one of the gate voltage required to decrease the threshold current by one orders due to the poor On/Off current ratio.
2.2.3 Determination of On/Off Current Ratio
Drain On/Off current ratio is another important factor of TFTs. High On/Off ratio represents not only large turn-on current but also small off current (or leakage current).
For large-scale AMLCD Pixel-TFTs, large Ion is required to fast charge Cpixel within 1 line time (generally demanded ≧10-6 A ), and small Ioff to maintain voltage on Cpixel for 1 frame time (≦10-12 A). As a result, we generally request that On/Off ratio can large than 106.
In our thesis, the on current is defined as the drive current when gate voltage at the maximum value and drain voltage fixed to |0.1V|. The off-current is specified as the minimum current when drain voltage equals to |0.1V|. Drain On/Off current ratio
In our thesis, the on current is defined as the drive current when gate voltage at the maximum value and drain voltage fixed to |0.1V|. The off-current is specified as the minimum current when drain voltage equals to |0.1V|. Drain On/Off current ratio