國 立 交 通 大 學
電子物理學系
碩 士 論 文
具高介電常數閘極絕緣層
之低溫多晶矽薄膜電晶體可靠度研究
Investigation on Reliability of LTPS-TFTs
With High-k Gate Dielectrics
指導教授 ：趙天生 博士
研 究 生 ：葉啟瑞
具高介電常數閘極絕緣層之低溫多晶矽薄膜電晶體
可靠度研究
Investigation on Reliability of LTPS-TFTs
With High-k Gate Dielectrics
指導教授 : 趙天生 博士 Advisor : Dr. Tien-Sheng Chao
研 究 生 : 葉啟瑞 Student : Chi-Ruei Yeh
國立交通大學
電子物理學系
碩士論文
A Thesis
Submitted to Department of Electrophysics
National Chiao Tung University
in Partial Fulfillment of the Requirements
for the Degree of Master of Science
in Electrophysics
July 2009
Hsinchu, Taiwan, Republic of China.
中華民國 九十八 年
I
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具高介電常數閘極絕緣層之低溫多晶矽薄膜電晶體
高介電常數閘極絕緣層之低溫多晶矽薄膜電晶體
高介電常數閘極絕緣層之低溫多晶矽薄膜電晶體
高介電常數閘極絕緣層之低溫多晶矽薄膜電晶體
可靠度研究
可靠度研究
可靠度研究
可靠度研究
指導教授 指導教授指導教授 指導教授 : : : 趙天生: 趙天生趙天生 趙天生 博士 博士博士 博士 研研 研研 究究究究 生生 生生 : : : : 葉啟瑞葉啟瑞葉啟瑞葉啟瑞 國立交通大學 國立交通大學國立交通大學 國立交通大學 電子物理 電子物理電子物理 電子物理學系學系學系學系 摘要 摘要摘要 摘要 在本論文中，我們製造了具有高性能之 P 型通道的高介電常數閘極絕緣層的 低溫薄膜電晶體並且探討其元件特性。為了能夠提升低溫薄膜電晶體的電性，我 們採用二氧化鉿（HfO2）作為閘極絕緣層以及引進新穎的結晶技術─金屬誘發 側向結晶法(MILC)─來製作高性能之元件。高載子遷移率約 215 cm2/V-s、優異 次臨界斜率約 107 mV/decade 以及低臨界電壓約-0.75 V 可被得到而不需要任何 的缺陷鈍化處理。 我們使用傳統直流(DC)電性量測技術來有系統地研究關於閘極負偏壓高溫 應力(NBTI)劣化機制，分別對於使用固相結晶法(SPC)與金屬誘發側向結晶法 (MILC)之二氧化鉿（HfO2）的低溫薄膜電晶體。在本實驗中，我們使用先前在 傳統二氧化矽(SiO2)上的閘極負偏壓高溫應力之經驗公式去分析高介電常數閘 極絕緣層的劣化機制。在閘極負偏壓高溫應力劣化下，實驗結果顯示閘極負偏壓 高溫應力(NBTI)的劣化主要是由於表面缺陷所造成，以及使用金屬誘發側向結晶 法(MILC)比起使用固相結晶法(SPC)的元件在可靠度方面有著更加穩定的性質。 最後，汲極效應在閘極負偏壓高溫應力劣化機制下亦被探討。結果顯示汲極 偏壓可以降低跨在閘極絕緣層的垂直電場，並且改善閘極負偏壓高溫應力所引起 的元件劣化。從實驗資料中，我們建立了汲極效應在閘極負偏壓高溫應力劣化的 理論模型。此模型與臨界電壓飄移(∆VTH)有良好的吻合因此能夠証實我們的理 論。
II
Investigation on Reliability of LTPS-TFTs
With High-κ
Gate Dielectrics
Advisors：：：：Dr. Tien-Sheng Chao Student：：：：Chi-Ruei Yeh
Department of Electrophysics National Chiao Tung University
Abstract
In this dissertation, high performance p-channel low temperature poly-silicon thin-film transistors (LTPS-TFTs) with high-κ gate dielectrics are fabricated and investigated. In order to enhance the characteristics of LTPS-TFTs, we adopted the employment of HfO2 gate dielectric and the novel crystallization methods,
metal-induced laterally crystallization (MILC), to fabricate high performance devices. High filed effect mobility µFE ~ 215 cm2/V-s, ultra-low subthreshold swing S.S. ~ 107
mV/decade, and low threshold voltage VTH ~ -0.75 V are derived from MILC-TFT
with HfO2 gate dielectric without any defect passivation methods.
Negative bias temperature instability (NBTI) degradation mechanism in solid-phase crystallization (SPC) and MILC LTPS-TFTs with HfO2 gate dielectric has
been studied systematically with a conventional DC measurement technique. We used the previously empirical formula for traditional NBTI in SiO2 to analyze the high-κ
gate dielectric in our experiment. The results showed that NBTI degradation is more dominated by the generation of interface trap states (NIT) and the MILC transistors
have more stability characteristic than SPC during the NBTI stress.
Finally, the drain bias effects on NBTI degradation mechanism is also investigated. The results showed that drain bias can reduced the vertical electric field
III
across gate dielectric and improved the NBTI-induced degradation. From experimental data, the NBTI model with drain bias effect is established. A good fit on the threshold voltage shift (∆VTH) prediction is obtained and confirms our theory.
IV
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在碩士班這短短的兩年多裡，因為受到了很多人的幫助，才會有今天的自己。 首先最要感謝我的指導教授─趙天生老師。謝謝老師能夠給予學生機會加入這個 大家庭，與實驗室夥伴一起成長和學習。老師高風亮節的學者風範，不論在學術 研究或是待人處世上都給予我莫大的助益，令我謹記在心。 接著，我要特別感謝馬鳴汶學長與江宗育學長。馬學長在我最無助時伸出援 手幫助我，並且細心教導我做實驗及研究，令我受益不少。即使畢業後到業界去 工作，仍不時著關心、指導我，給予我很多幫助，在此衷心的感謝。江學長耐心 的一步步帶著我做實驗，同時也教導我很多研究以外的東西，這一年多來受到你 很多的照顧，亦致上由衷的謝意。此外，感謝王冠迪學長在量測分析方面的指導， 令我學到很多，受益非淺。還要感謝碩士生涯期間，實驗室眾多學長姐、同學與 學弟妹的照顧與相互扶持，令我的研究生活充滿了歡樂與色彩。這其中包括了： 郭柏儀學長、高國興學長、呂宜憲學長、呂侑倫學長、林哲緯學長、蔡孟岐學長、 廖家駿學長、吳翊鴻學長、林威良學長、王智盟學長、顏榮家學長…等；同學： 士安、才民、玉喬、繁達、聖賢…等；以及學弟妹：時璟、聿民、政昌、岷臻、 琬琦…等，感謝你們陪伴我度過這兩年多來的點點滴滴，在我人生歷程中留下很 重要的一頁，謝謝你們。 最後，我要致上最深的謝意給我的父母─葉定國先生、黃阿綢女士。因為有 你們的不辭辛勞的養育、栽培與鼓勵，使我能在良好的環境下完成學業，在此再 度獻上最誠摯的謝意與祝福。V
Contents
Abstract (Chinese)………...………...Ⅰ Abstract (English)……….…………...…………...Ⅱ Acknowledgements (Chinese)……….………..……….…….Ⅳ Contents……….…..………....Ⅴ Table Caption……….………..…………....Ⅶ Figure Caption……….………..……….ⅦChapter 1 Introduction
1.1 Overview of Polycrystalline Silicon Thin-Film Transistors…...1
1.2 LTPS-TFTs with High-κ Gate Dielectric………..……….……….3
1.3 Overview of Metal-Induced Lateral Crystallization……….…………...4
1.3.1 Development of History………..………...……….5
1.3.2 Formation Mechanism………..……….6
1.4 Negative Bias Temperature Instability in LTPS TFTs……….….……….8
1.5 Reliability Issue on High-κ Gate Dielectric...………..10
1.6 Motivation……….……..………...11
1.7 Dissertation Organization……….……..………..13
Chapter 2 Device Fabrication and Method of Parameter Extraction
2.1 Device Fabrication………....………262.2 Method of Parameter Extraction………...…..……….27
2.2.1 Determination of Threshold Voltage………..……..…….27
2.2.2 Determination of Subthreshold Swing………..………28
2.2.3 Determination of On/Off Current Ratio………..………..29
2.2.4 Determination of Field Effect Mobility………..………...30
VI
Chapter 3 Electrical Characteristics of High Performance SPC and
MILC P-Channel LTPS-TFT with High-κ
κ
κ
κ Gate Dielectric
3.1 Introduction………..……….38 3.2 Results and Discussion……….………..………...39 3.3 Summary………..………..40
Chapter 4 Negative Bias Temperature Instability in SPC and MILC
P-Channel LTPS TFTs with HfO
2Gate Dielectric
4.1 Introduction………..………….………48 4.2 Results and Discussion……….………..………….………..50 4.3 Summary………..……….……….55
Chapter 5 Drain Bias Effects on Negative Bias Temperature
Instability in LTPS TFTs With HfO
2Gate Dielectric for
SPC and MILC Devices
5.1 Introduction………..………….………75 5.2 Results and Discussion……….………..………….………..77 5.3 Summary………..……….……….81
Chapter 6 Conclusions
6. Conclusions……….………..………..95
VII
Table Caption
Chapter 3
Table.I Important device parameters of SPC and MILC LTPS-TFTs with HfO2 gate
dielectric. The others’ works are also listed for comparison.
Figure Caption
Chapter 1
Fig. 1 MILC polysilicon formation during annealing process. Fig. 2 MILC polysilicon formation mechanism.
Chapter 2
Fig. 1 The process flow of SPC LTPS-TFTs with HfO2 gate dielectric.
Fig. 2 The process flow of MILC LTPS-TFTs with HfO2 gate dielectric.
Chapter 3
Fig. 1 The transfer characteristics (ID-VG and Gm) of SPC and MILC LTPS-TFTs
with HfO2 gate dielectric.
Fig. 2 The gate capacitance of Al/HfO2/p-Si capacitor.
Fig. 3 The plots of ln [ID/(VG – VFB)] versus 1/(VG – VFB)2 curves at VD = –0.1 V
and high VG.
Fig. 4 The ID-VD curve of SPC and MILC LTPS-TFTs with HfO2 gate dielectric.
Chapter 4
Fig. 1. Transfer characteristics of (a) SPC and (b) MILC LTPS-TFTs with HfO2 gate
VIII
Fig. 2. Output characteristics of (a) SPC and (b) MILC LTPS-TFTs with HfO2 gate
dielectric before and after NBTI stress.
Fig. 3. Dependence of the threshold voltage shift (∆VTH) versus stress time at 25℃
with the (a) SPC and (b) MILC device.
Fig. 4. Dependence of the threshold voltage shift (∆VTH) versus stress time at 50℃
with the (a) SPC and (b) MILC device.
Fig. 5. Dependence of the threshold voltage shift (∆VTH) versus stress time at 75℃
with the (a) SPC and (b) MILC device.
Fig. 6. Dependence of the threshold voltage shift (∆VTH) versus stress time at 100℃
with the (a) SPC and (b) MILC device.
Fig. 7. Dependence of the threshold voltage shift (∆VTH) versus stress voltage at
various temperature with the (a) SPC and (b) MILC device.
Fig. 8. Dependence of the threshold voltage shift (∆VTH) versus temperature at
various stress voltage with the (a) SPC and (b) MILC device.
Fig. 9. Dependence of the (a) threshold voltage shift (∆VTH) and (b) ION degradation
versus temperature on the same overdrive stress voltage with the SPC and MILC device.
Fig. 10. Dependence of the transconductance degradation (%GM) versus stress time
at 100℃ with the (a) SPC and (b) MILC device.
Fig. 11. Dependence of the subthreshold swing degradation (%S.S.) versus stress time at 100℃ with the (a) SPC and (b) MILC device.
Fig. 12. Dependence of the transconductance degradation (%GM) versus stress
voltage at various temperature with the (a) SPC and (b) MILC device. Fig. 13. Dependence of the transconductance degradation (%GM) versus temperature
at various stress voltage with the (a) SPC and (b) MILC device.
IX
voltage at various temperature with the (a) SPC and (b) MILC device. Fig. 15. Dependence of the subthreshold swing degradation (%S.S.) versus
temperature at various stress voltage with the (a) SPC and (b) MILC device.
Chapter 5
Fig. 1. Transfer characteristics of (a) SPC and (b) MILC LTPS-TFTs with HfO2 gate
dielectric under constant stress gate voltage (VG_STRESS) and various stress
drain voltage (VDS_STRESS).
Fig. 2. Output characteristics of (a) SPC and (b) MILC LTPS-TFTs with HfO2 gate
dielectric under constant stress gate voltage (VG_STRESS) and various stress
drain voltage (VDS_STRESS).
Fig. 3. Dependence of the threshold voltage shift (∆VTH) versus stress time at 25℃
under various VDS_STRESS with the (a) SPC and (b) MILC device.
Fig. 4. Dependence of the threshold voltage shift (∆VTH) versus stress time at 50℃
under various VDS_STRESS with the (a) SPC and (b) MILC device.
Fig. 5. Dependence of the threshold voltage shift (∆VTH) versus stress time at 75℃
under various VDS_STRESS with the (a) SPC and (b) MILC device.
Fig. 6. Dependence of the threshold voltage shift (∆VTH) versus stress time at 100℃
under various VDS_STRESS with the (a) SPC and (b) MILC device.
Fig. 7. Dependence of the threshold voltage shift (∆VTH) versus stress time at (a)25℃
and (b)100℃ on the SPC device.
Fig. 8. Schematic of the NBTI stress with drain bias, showing the reduction of gate oxide electrical field along the channel.
Fig. 9. Measured (solid dot) and predicted (dotted line) threshold voltage shift (∆VTH) as a function of drain bias at various temperature.
X
Fig. 10. Dependence of the (a) transconductance degradation (%GM) and (b)
subthreshold swing degradation (%S.S.) versus drain bias at various temperature with the SPC device.
1
Chapter 1
Introduction
1.1 Overview of Polycrystalline Silicon Thin-Film Transistors
Thin film transistors (TFTs), which employ a thin semiconductor film on an insulating substrate as the active device channel, was first demonstrated in 1961 by Dr. P. K. Wenimer in RCA. With its simplicity in structure and fabrication, it becomes more and more popular for the application of thin film transistors in image sensors and displays. In recent years, the flat display are widely used in advanced electronic products, such as cellular phone, portable computer, digital camera, etc. In all types of flat-panel displays, active-matrix liquid crystal displays (AMLCDs) are one of the most promising candidates in high quality large-area flat-panel displays due to higher refresh rate compared with the conventional passive-matrix displays [1.1]-[1.3]. Besides, TFTs also has been investigated and developed on many electric components, such as static random access memory (SRAM), dynamic random access memory (DRAM) [1.4][1.5], and 3-D ICs’ applications [1.6].
It has been known that hydrogenated amorphous silicon (α-Si:H) TFTs were widely used for the pixel switching device of AMLCDs in LCD industry [1.7]. There are many advantages on α-Si:H TFTs, such as their compatibility with low processing temperature on the large-area glass substrates and high off-stated impedance which result in low leakage current. However, its driving current and electron field effect mobility µEF is very low (below 1 cm2V-1sec-1) to limit their application for AMLCDs
technology only to the switching elements. It is very desirable to integrate the switching elements with the driver circuits together on the same substrate, because it is not only to reduce the cost but also to improve circuit and system reliability.
2
instead of amorphous silicon for the active element of LCDS [1.8]-[1.10]. Because the field effect mobility µEF and turn-on current in poly-Si is significantly higher than that
in amorphous silicon, the poly-Si TFTs has a larger aperture ratio and higher panel resolution. However, there is a new problem for poly-Si TFTs. Low temperature process is must because the switch device is required to embed on the glass substrate for application of displays. For the general display-glass, maximum processing temperature needs to be kept below 600℃. Moreover, low temperature process also limits and affects other critical process steps, such as gate insulator formation and the activation of the doped regions of the device. These reasons imply that we should develop new technologies for low temperature polycrystalline-silicon thin-film transistor (LTPS-TFTs) [1.11]-[1.15].
Generally, growing poly-Si films by low temperature chemical vapor deposition (LPCVD) will get the small grain sizes and result in poor characteristics in ploy-Si TFTs. In order to further enhance TFTs characteristics, several techniques to increase the grain size of LTPS-TFTs have been proposed and developed, such as solid-phase crystallization (SPC) , excimer laser annealing (ELA), and metal-induced lateral crystallization (MILC) [1.16]-[1.18]. In addition, the performance of poly-Si TFTs is strongly influenced by defects such as dangling bonds and strained bonds located at the grain boundaries [1.19]. Those defects would trap carriers and generate a potential barrier which degrades the electrical properties. To reduce the impact of the existing defects, a good way is passivated them. Plasma treatment or passivation by ion implantation could effectively repair week bonds and create strong bonds, which can enhance the performance and reliability of LTPS-TFTs [1.19]-[1.33].
Recently, system-on-panel (SOP) and three-dimension integration of integrated circuit (3-D ICs) technology are attracting much attention to realize on LTPS-TFTs’ applications. SOP means that to integrate the switching elements with the driver
3
circuits together on the same substrate [1.34]. It can help to reduce the cost and improve circuit and system reliability. The 3-D ICs’ technology can enhance chip area which can reduce cost of TFT devices. Therefore, the idea of system-on-panel and three-dimension integration would be a novel development of semiconductor industry.
1.2 LTPS-TFTs with High-κ Gate Dielectric
Recently, low temperature polycrystalline-silicon thin-film transistors (LTPS-TFTs) have been widely used in active-matrix liquid crystal displays (AMLCDs) due to their better performance in polysilicon than in amorphous silicon. For realizing system-on-panel (SOP) to LTPS-TFTs [1.34], integrating driving ICs on the glass substrate are required necessarily. Therefore, high-performance TFTs with high driving current IDsat, low gate leakage current IG, low threshold voltage VTH and
excellently subthreshold swing S.S. are required.
For achieving this goal, a thin gate oxide be used to increase the gate capacitance density to enhance the driving current. However, scaling down the gate oxide may induce higher gate leakage current due to the thinner thickness of gate dielectric. In order to preserve the physical dielectric thickness while increasing the gate capacitance, several high-κ dielectrics have been proposed such as Al2O3, Ta2O5,
Pr2O3, HfO2, etc [1.35]-[1.38]. Among above-mentioned dielectric material, HfO2 is
one of the most potential candidates recently due to its high permittivity (14-20) and thermal stability with poly-Si. However, the high IG may be resulted by higher
temperature annealing due to poly-crystalline HfO2 [1.39]-[1.41].
In addition, low quality deposited low-temperature SiO2 (like PECVD-SiO2) is
generally employed as the gate dielectric of the conventional LTPS-TFTs. The poor interface between the gate dielectric and silicon substrate, due to the limitation of low temperature process, has been observed [1.11]-[1.15]. Comparing with low quality
4
SiO2, low temperature deposited high-κ gate could have better interface quality and
electrical characteristic. Unlike in single crystal Si MOSFET, there are maybe some differences in the world of LTPS-TFTs with high-κ gate dielectric.
1.3 Overview of Metal-Induced Lateral Crystallization
Low temperature polycrystalline-silicon thin-film transistors (LTPS-TFTs) have been attracted to use in various fields such as active-matrix liquid crystal displays (AM-LCDs), solar cells, and three-dimensional (3-D) integrated circuit [1.6]. The fabricating high-performance LTPS-TFTs enables their use in a wide range of applications. Therefore, there is great interest in improving the performance of LTPS-TFTs. To fabricate large grain sizes of poly-Si on common glass substrate, the most widely used method is to deposit α-Si film and recrystallize by post-annealing, such as solid-phase crystallization (SPC) [1.42][1.43], excimer laser annealing (ELA) [1.44][1.45], and metal-induced lateral crystallization (MILC) [1.46][1.47]. In general, poly-Si layer was not founded using to deposit directly by low temperature chemical vapor deposition (LPCVD) because the grain size is too small compared to the size of transistor.
Conventionally, SPC is a common method of crystallizing α-Si. It has many advantages, such as simplicity, low cost and batch process. But the crystallization temperature is too high (around 600℃) for commercial glass substrates. By localizing the high temperature to the silicon layer, ELA can be considered a ‘‘low’’ temperature process. While it is capable of producing poly-Si film with low defect densities, it suffers from several problems such as high initial cost and high process complexity. Recently, metal-induced lateral crystallization (MILC) phenomenon was reported for successfully producing the low temperature (around 500℃) fabrication of high quality poly-Si films and high performance TFTs. This method is simple and can be
5
integrated into CMOS technology. Unlike ELA, MILC is a low cost batch process; unlike SPC, better quality poly-Si film due to its large grain size and longitudinal grain boundaries.
1.3.1 Development of History
When some metal are added into α-Si, the crystallization temperature can be lowered below 600℃, and this phenomenon is known as metal-induced crystallization (MIC). This has been reported for various metal and they can be classified into two groups. One is eutectic-forming metal such as Ag, Au, Al, Sb, and In; the other is silicide-forming metal such as Pd, Ti, Cu, and Ni. Among various metal, Ni has been shown to be the best candidate due to the NiSi2 has a small lattice mismatch of 0.4%
with c-Si [1.48]. However, device fabricated by MIC process has poor electrical properties because of metal contamination at the channel region. Beside, the grain size of MIC is too small. It is believed that the electrical properties of TFTs can be improved if the grain size of the poly-Si can be enhanced and number of grain boundaries in the channel region can be minimized.
Recently, a new method which can solve this problem called metal-induced lateral crystallization (MILC). This method is able to produce successfully large free region of metal contamination to poly-Si thin film while have better crystallization quality. MILC-TFTs have largely longitudinal grains and their boundaries are longer ‘‘parallel’’ with the flow of carriers [1.49]. Unlike SPC with a columnar grain structure randomly, there are many grain boundaries which are transverse to Id. The
presence of potential barrier cause the additional scattering at the grain boundaries and result in µFE degradation [1.50][1.51]. In addition, the laterally long grain size is
over several tens of microns which are sufficient for the size of transistor.
6
the continuous grain boundaries across the channel [1.47][1.52]. They exist in the three parts: source and drain (S/D) junction edge near the channel and in the central region of channel. At the S/D junction edge, which is the overlap between MIC/MILC boundaries, has high density of grain boundary trap states and crystalline defects; there is also the same large defects in the central region between MILC/MILC boundaries. It has been known that PN-junction leakage current can arise by electron-hole pairs generated via grain boundary traps in the depletion region, particularly at drain edge of the channel. In order to solve this problem, removing the MIC/MILC boundaries from junction is necessary. Ni-offset TFT structure has been fabricated for this problem [1.52][1.53]. Although Ni-offset deposition method could exclude MIC/MILC boundaries from the edges of the channel, the MILC/MILC boundary remained at the center of channel.
Finally, a novel and smart technology called metal-induced unilateral crystallization (MIUC) is presently proposed [1.47][1.54]. MIUC not only retains the essentially longitudinal MILC grain structures, it also removes all major grain boundaries — including the MILC/MILC boundary — from the edges of junction and channel. Compared to the conventional MILC TFTs, the new MIUC devices are shown to have higher field effect mobility µFE, better subthreshold swing S.S. and
significantly reduced leakage current [1.55]. All of these positive characters show that MIUC is a particularly suitable technology for system on penal (SOP) applications with low-temperature process TFTs.
1.3.2 Formation Mechanism
During the MIC annealing process (around 500℃), Ni deposited onto the seed window would diffuse into the α-Si film and react with silicon to from a nickel silicide (NiSi2) . The NiSi2 precipitates act as a good nucleus of Si, because which has
7
similar crystalline structure and small lattice mismatch of 0.4% with Si. Thus, α-Si under the silicide is crystallized into polysilicon during annealing process and this is called metal-induced crystallization (MIC) [1.56][1.57]. For the SPC process, it is typically carried out by furnace annealing around 600℃ because this temperature can permit to begin forming a steady-state of nucleation enough to crystallize. For this reason, adding some Ni into a-Si layer can lower the crystallization temperature below 600℃.
In the MIC region, there are many grains and grain boundaries at MIC polysilicon layer. These grain boundaries provide good locations for trapping the atoms. Due to the fast nickel diffusion in crystalline silicon structure and good nickel trapping property at the crystalline silicon to α-Si interface, most of Ni atoms in the MIC region diffuse to and are trapped at the grain boundaries. At the MIC/α-Si interface, the nickel silicide boundaries form and exist as a continuous sandwich layer between MIC/α-Si as illustrated in Fig. 1 and Fig. 2 [1.58]. This thin nickel silicide layer is called reactive grain boundary (RGB), which is responsible for the grain growth for MILC. During the continuous annealing after MIC, some of extra nickel atoms will diffuse and reach toward the front of RGB region. The nickel atoms will lower the activation energy of α-Si crystallization and react with lateral α-Si region to form the new silicide layer. Simultaneously, the silicon atoms are dissociate at the back of nickel silicide RGB and then form crystalline silicon (c-Si) region, which is the MILC polysilicon. The dissociated nickel atoms again diffuse to the α-Si region and construct the new nickel silicide continuously, which leads the shift of nickel silicide RGB and the growth of MILC polysilicon. As a result, the α-Si is crystallized to polysilicon in the lateral direction, and this process is called metal-induced lateral crystallization (MILC). The Ni content in the MILC area is about 0.02 atomic %, and the higher concentration is observed at RGB region (0.4%) and MIC region [1.58].
8
Crystallites are formed randomly by the background SPC during the MILC annealing process [1.59]. Although the temperature is below 600℃, the nucleation probably occurs due to the long annealing time. Once random crystallites are formed, an additional energy is required to break the crystalline bonding structure to restore α-Si atoms which can be recrystallized by MILC. The occurrence of SPC will let lateral crystallization slow down or even stop by the random polysilicon grains resulting from the SPC. Thus, the annealing temperature is the key for the longer lateral MILC polysilicon. Although a faster MILC rate can be accomplished by using a higher annealing temperature, the shorter maximum lateral crystallization length can also be obtained [1.59]. In addition, the MILC growth not only depend on the annealing temperature but also be affected by the dopant and thickness of silicon substrate [1.60][1.61].
1.4 Negative Bias Temperature Instability in LTPS TFTs
Negative bias temperature instability (NBTI) occur mainly in p-channel MOS device, which stressed with negative gate bias and elevated temperature. In general, devices will degrade during the long-time operation, and cause the system to fail. It obviously degraded electrical characteristic like an increase in absolute threshold voltage (VTH) and degradations in drive current (ID) or channel transconductance (GM)
[1.62][1.63]. As a results, we widely used the BTI stress to accelerate testing the device lifetime on the high electric field across gate dielectric. Typical stress temperature lie in the 100℃–250℃ range with oxide electric fields below 6MV/cm.
The NBTI-induced degradation is mainly attributed to the generation of interface trap states (NIT) and can be partially recoverable once the stress bias is removed. This
phenomenon has been interpreted by the reaction-diffusion (R-D) model [1.64][1.65]. During the stress, inversion layer holes interact with Si–H bonds and dissociated at
9
Si/SiO2 interface. Subsequently, the released hydrogen species either diffuse away
from the Si/SiO2 interface and leaves behind Si– (NIT generation), or reacts back with
Si- and form Si–H (NIT passivation). The NIT generation will cause device
degradation. In addition, some reports indicated that a portion of NBTI-induced degradation is recoverable [1.66][1.67]. This partially recoverable degradation is caused by hydrogenic depassivation (recombine with Si–) when the stress removed or reduced. The relaxation characteristics can be caused by the delay time between the end of stress and the VTH measurement and Id – Vg measurement time, which may
result in an erroneous estimation of a device lifetime.
Low-Temperature polycrystalline silicon thin film transistors (LTPS TFTs) are attracting much research interest as potential candidates for the realization of system on panel (SOP), which indicated LTPS TFTs must be designed using the COMS inverter configuration. During the COMS operation, p-channel TFT will be subjected to negative bias stress when input is at a low voltage level and output is at a high voltage level. Besides, it must be noted that the poor thermal conductivity of the glass substrate in LTPS TFTs. From the fabrication-technology point of view and as a long-term reliability concern, the stability of poly-Si TFTs is of significant importance. That are why the NBTI is important and interested in the reliability issues of LTPS TFTs.
In MOSFET, the NBTI degradation is mainly attributed to generation of interface trap states (NIT). In LTPS TFTs, however, the extra defects and grain boundaries in the
poly-Si channel region , more Si-H bonds existence due to CVD deposition process, and the poor quality at SiO2/poly-Si interface by low temperature process limitation,
may be different results that in MOSFETs. The main degradations in LTPS TFTs could divide into three parts: gate dielectric film, effective interfacial layer of SiO2/poly-Si, and poly-Si channel film. For example, the carrier injection into the gate
10
dielectric would result in threshold voltage VTH shift; the degradation of interfacial
layer of SiO2/poly-Si and channel film may cause low field effect mobility µFE, high
subthreshold swing S.S. and drain leakage current Imin.
Besides, in order to enhance TFTs characteristics, numerous techniques to increase the grain size of poly-Si film have been proposed and developed, such as Solid-Phase Crystallization (SPC), Excimer Laser Crystallization (ELC) and Metal-Induced Lateral Crystallization (MILC) [1.42]-[1.47], but the compared reliability effects of them are rarely explored for LTPS TFTs. Furthermore, some hydrogen-related plasma treatments have been proposed to improve the electrical characteristics of TFTs. The improvement of TFTs is due to the defects passivation of grain boundaries and interface at SiO2/poly-Si. Nevertheless, the introduction of
hydrogen would result in the reliability issue.
For reasons mentioned above, the NBTI issue in LTPS TFTs is worthwhile to discuss closely. This subject will be discussed further in later chapters.
1.5 Reliability Issue on High-κ Gate Dielectric
Recently, several high-κ gate dielectrics have been investigated as replacements for the SiO2 gate dielectric. It allows us keeping the same EOT to increase the
physical thickness of the gate stack. Hence, the gate leakage is found to be reduced by 2 to 3 orders of magnitude [1.68]. Hafnium based dielectrics have been demonstrated as promising candidates for advanced high-κ gate stacks [1.68][1.69], and it was claimed that they are finally ready to be implemented in 45nm technology and beyond.
However, those high-k materials might not be sufficiently stable under the stress. Compared to SiO2 , hafnium-based oxide showed a large amount of VTH shift due to a
11
introduces grain into the gate stack and adds extra trap states [1.68]-[1.70]. These pre-existing traps cause the VTH instability due to charge trapping/de-trapping
phenomenon [1.71][1.72]. Some also reported that a thinner HfO2 film demonstrates
less VTH shift due to less trapping in the bulk high-κ layer [1.69]. Consequently, one
of the challenges in the implementation of these high-κ dielectrics is the stress-induced instability behavior.
In addition, similar to the conventional NBTI recovery in the high-κ dielectric, the lifetime evaluation methodology for the high-κ gate dielectrics may need to be redefined because a significant portion of the charge trapping/de-trapping in high-κ gate dielectric is observed [1.70][1.73]. Since the switching time between the stress and sense measurements and the sensing time are usually on the order of a second, conventional measurements would severely underestimate VTH instability in high-κ
devices. As a result, the single pulse Id-Vg measurement technique [1.73][1.74]
developed to minimize trap charging/discharging during stress interruption time has previously been applied to BTI studies.
1.6 Motivation
Recently, to realize system-on-panel (SOP) for LTPS-TFTs on the glass substrate are expected. In order to achieve high function integrated circuits, high-performance TFTs with high driving current, low gate leakage current, low threshold voltage VTH
and low subthreshold swing S.S. are required. However, it is the difficult challenge to develop high-performance devices for both pixel TFTs and driving circuits. For resolving this problem, we adopt novel crystallization method named metal-induced lateral crystallization (MILC) to enlarge poly-Si grain size to decrease the grain boundaries and defects. MILC is superior to conventional SPC due to it have a better quality poly-Si film. In addition, we also used the high-k material, HfO2, to replace
12
the conventional SiO2 as gate dielectric. A large gate capacitance density with the
same physical thickness by using high-k gate dielectric can attract more carries with a smaller voltage to turn on the LTPS TFTs. By combining the two novel technologies, we expect to develop the high-performance devices on LTPS-TFTs.
Furthermore, we also study the reliability issues on high-performance LTPS-TFTs with HfO2 gate insulator and MILC channel. For the viewpoint of
produces, the long-term stability is significantly important. It has been reported that LTPS-TFTs suffer from several degradation mechanism, such as negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), hot-carrier stress (HCS), and so on. Therefore, the degradation characteristic and mechanism of LTPS-TFTs under dc stress test must be investigated for next-generation of panel application. However, reliability issues are still not thoroughly studied in LTPS-TFTs with HfO2 gate dielectric. In addition, many circuit
applications require transistors to operate at high drain bias in addition to a high gate bias. It was found that the BTI characteristics in MOSFETs are strongly affected by the drain bias (VDS) during the stress. As a result, using the BTI stress to accelerate
testing the device lifetime may cause an erroneous estimation of a device lifetime. Therefore, it is critical to understand the effect of drain bias on BTI degradation mechanism, and its impact on the circuit reliability at the operation condition.
In this work, we investigate the reliability mechanism of p-channel devices with HfO2 gate dielectric. Besides, we also discuss differences between SPC and MILC
LTPS-TFTs on degradation mechanism. Based on the experimental results, we hope to clarify the degradation characteristic and their mechanisms.
13
1.7 Dissertation Organization
In chapter 1, some backgrounds about LTPS TFT is introduced in this section : overview of poly-Si TFTs; LTPS TFTs with high-k gate dielectric; overview of metal-induced lateral crystallization; negative bias temperature instability in LTPS TFTs; and reliability issue on high-κ gate dielectric.
In chapter 2, we describe the device fabrication and the methods to extract the typical characteristic parameters of LTPS-TFTs in our experiment.
In chapter 3, electrical characteristics of high performance SPC and MILC p-channel LTPS-TFT with HfO2 gate dielectric are characterized, for comparison.
In chapter 4, the NBTI degradation mechanism in LTPS TFTs with HfO2 gate
dielectric has been investigated with a conventional DC measurement technique. Besides, the reliability comparisons for SPC and MILC devices have been studied systematically.
In chapter 5, the drain bias effect on negative bias temperature instability (NBTI) degradation mechanism in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) with high-k gate stack is analyzed by the DC measurement technique. In addition, the NBTI model with drain bias effect is established.
14
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[71] D. Heh, C. D. Young, and G. Bersuker, “Experimental Evidence of the Fast and Slow Charge TrappingDetrapping Processes in High-k Dielectrics Subjected to PBTI Stress,” IEEE Trans. Electron Devices, vol. 29, no. 2, pp. 180-182, 2008.
[72] R. Choi, S. J. Rhee, J. C. Lee, B. H. Lee, G. Bersuker, “Charge trapping and detrapping characteristics in hafnium silicate gate stack under static and dynamic stress,” IEEE Trans. Electron Devices, vol. 26, no. 3, pp. 197-199, 2005.
[73] D. Heh, R. Choi, C. D. Young, G. Bersuker, “Fast and slow charge trappingdetrapping processes in high-k nMOSFETs.,” Integrated Reliability Workshop Final Report, 2006.
[74] R. Choi, S. C. Song, C. D. Young, G. Bersuker, “Charge trapping and detrapping characteristics in hafnium silicate gate dielectric using an inversion pulse measurement technique,” Applied Physics Letter, 87, 122901, 2005.
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(a) Before annealing
(b) After annealing and MIC region formed
(c) After annealing and MILC region formed
25
26
Chapter 2
Device Fabrication and Method of Parameter Extraction
In this thesis, high performance p-channel low temperature poly-silicon thin-film transistors (LTPS-TFTs) are fabricated by the employment of HfO2 gate dielectric and
two crystallization methods, solid phase crystallization (SPC) and metal-induced laterally crystallization (MILC), for comparison. In addition, we will introduce the methods to extract the typical characteristic parameters of LTPS-TFTs, such as threshold voltage VTH, subthreshold swing S.S., drain current ON/OFF ratio, field
effect mobility µEF, and the trap state density Ntrap. All the electrical characteristics
were measured by Keithley 4200-SCS.
2.1 Device Fabrication
As shown in Fig.1 and Fig.2, the fabrication of devices started by depositing a 50-nm undoped amorphous Si (α-Si) layer at 550°C and 120m torr in a low-pressure chemical vapor deposition system on Si wafers capped with a 500-nm thermal oxide layer. For SPC LTPS-TFT, the 50-nm α-Si layer was crystallized by SPC process at 600°C for 24-h in a N2 ambient. For MILC LTPS-TFT, a 5-nm Ni was deposited by
electron-beam evaporation system at room temperature, 10-6 torr base pressure and 10-5 torr process pressure, and patterned by lift-off process as a seed layer to crystallize the α-Si. Then the 50-nm α-Si layer was crystallized by MILC process at 550°C for 24-h in a N2 ambient, and the residual Ni was removed by H2SO4 + H2O2
solution. Here, both SPC and MILC poly-silicon channel films have been formed. Then a 500-nm plasma-enhanced chemical vapor deposition (PECVD) oxide was deposited at 300°C for device isolation. The device active region was formed by patterning and etching the isolation oxide. The source and drain regions (S/D) in the
27
active device region was implanted with boron (10 keV at 5 x 1015 cm-2). The S/D was activated at 600°C for 24-h annealing in a N2 ambient. A 50-nm HfO2 was deposited
by electron-beam evaporation system at room temperature, 10-6 torr base pressure and 10-5 torr process pressure. An O2 annealing in furnace was applied to improve the
HfO2 at 400°C for 30-min. In order to compare the HfO2 gate dielectric, a 50-nm
PECVD SiO2 was also deposited at 300°C in SPC poly-silicon channel film. After the
patterning of S/D contact holes, aluminum was deposited by thermal evaporation system at room temperature, 10-6 torr base pressure and 10-5 torr process pressure, as the gate electrode and S/D contact pad. Finally, the TFT devices were completed by the contact pad definition. All process flow is shown in Fig. 1 and Fig.2 . Devices with gate width (W) and length (L) of 10µm /10µm are measured.
2.2 Method of Parameter Extraction
2.2.1 Determination of Threshold Voltage
Threshold voltage VTH is an important parameter of semiconductor devices.
However, various definitions for VTH have been proposed on different types of device.
In MOSFET, there are two common methods for determination of VTH. One is the
linear extrapolation method, which is defined in “linear-scale” ID-VGS curves at a low
drain voltage (50~100mV). According to ideal ID vs. VGS equation
(1)
(2)
We have to note that equation (2.2) is accurate only for negligible series resistance like source and drain resistance RSD, which can be generally negligible at
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Gm,max, which is common practice to find the point of maximum slope of the IDS-VGS
curve (
!) and fit a straight line to extrapolate at ID=0. The real
ID-VGS curve deviates from a straight line at gate voltage below VTH due to
subthreshold current, and above VTH due to series resistance and mobility degradation
effect. Hence the VTH is determined from the extrapolated intercept of gate voltage
(VGS) at ID=0 by
"#$
(3)
In our thesis, VTH is defined differ from above description and is defined by
more simply way which called constant drain current method. This method can be found in almost the papers relate to poly-Si TFTs. The VTH obtained from this way is
close to the another extracted from linear extrapolation method. Here, constant drain current is fixed to when I = (W/L)*100 nA for p-channel at VDS=|0.1|V and W, L are
channel width and length respectively. In this thesis, devices were all measured by W=10 µm, L=10 µm. Thus, Ids was fixed to 10-7 A in all our discussion.
2.2.2 Determination of Subthreshold Swing
Subthreshold slope (S.S.) is a typical parameter to describe the control ability of gate toward channel, which reflects the turn on/off speed of a device. It is defined as the amount of gate voltage required to increase/decrease drain current by one order of magnitude.
The S.S. should be independent of drain voltage and gate voltage. In reality, however, the S.S. increases with drain voltage due to channel shortening effect such as charge sharing, avalanche multiplication and punchthrough effect. The subthreshold slope is also related to gate voltage due to undesirable and inevitable factors such as the serial resistance and interface states. In LTPS-TFTs, the
29
subthreshold swing is also dependent on defects and grain boundaries in ploy-Si channel films. It has been reported that S.S. be closely related to the trap states located near the mid-gap (deep states), which originate from dangling bonds [2.1]. Besides, because of the limitation of low temperature process, the poor interface between the gate dielectric and silicon substrate has been observed. Both bulk and interface traps would make poor S.S. in LTPS-TFTs. The formula of subthreshold slope were defined as
%& %& '()*+,#$
("-$ .
/ (4)
In our thesis, the S.S. is defined as one-half of the gate voltage required to decrease the threshold current by two orders of magnitude. In some of stress conditions, the S.S. is defined as one of the gate voltage required to decrease the threshold current by one orders due to the poor On/Off current ratio.
2.2.3 Determination of On/Off Current Ratio
Drain On/Off current ratio is another important factor of TFTs. High On/Off ratio represents not only large turn-on current but also small off current (or leakage current). For large-scale AMLCD Pixel-TFTs, large Ion is required to fast charge Cpixel within 1
line time (generally demanded ≧10-6 A ), and small Ioff to maintain voltage on Cpixel
for 1 frame time (≦10-12 A). As a result, we generally request that On/Off ratio can large than 106.
In our thesis, the on current is defined as the drive current when gate voltage at the maximum value and drain voltage fixed to |0.1V|. The off-current is specified as the minimum current when drain voltage equals to |0.1V|. Drain On/Off current ratio can be given as following
,01
,022
3456787946:;899<:=4=">?@A&"@
30
2.2.4 Determination of Field Effect Mobility
Usually, field effect mobility (µeff) is determined from the maximum value of
transconductance (Gm) at low drain bias. The transfer characteristics of Poly-Silicon
TFTs are similar to those of conventional MOSFETs, so that the first order of I-V relation in the bulk Si MOSFETs can be applied to Poly-Silicon TFTs. The drain current in linear region (VDS < VGS -VTH) can be approximated as the following
equation:
B<CCD*5EF
GH
(6)
where W and L are channel width and channel length, respectively. Cox is the gate
oxide capacitance per unit area and VTH is the threshold voltage. Thus, the
transconductance is given by
I7 (,#$
("-$ B<CCD*5E F
GH (7)
Therefore, the field-effect mobility is B<CC G
;0JF"#$I7745 K"#$LA (8)
2.2.5 Determination of The Trap Density
In LTPS-TFTs, the trap state density (Nt), which originate from dangling binds
or strained bonds ,located in the grain boundaries of poly-Si film. It will trap carrier and generate barrier height VB to degrade carriers transportation like reduction of field
effect mobility (µeff). Besides, it also make higher threshold voltage VTH, subthreshold
swing S.S., and leakage current. Because the electrical transport properties of poly-Si films are strongly influenced by carrier trapping at the grain boundaries, we can base on this mechanisms to extract the trap state density (Nt) from the ID-VGS
31
Many researchers have studied the electrical characteristics and carrier transport in poly-Si TFTs [2.2] [2.3]. According to the sample grain boundary trapping model, Seto et al. have successfully used this model to describe the dependence of the conductivity of poly-Si on trap density in 1975 [2.2]. They defined the barrier height VB and developed the current transport mechanisms by thermionic emission over the
barrier. Later, Levinson in 1982 based on the Seto model to propose the basic current equation of poly-Si TFTs, which assumed that scattering of carriers take place only at grain boundaries [2.4]. By modifying the mobility µb and replacing the doping
concentration with gate induced charge density NG, the correct expression for the I-V
characteristics at low drain voltage in poly-Si TFTs is very similar to that in regular MOSFET’s. It is given by
BAD*5F
G MNO E
PQRST=UV
WX YZ;0J"-/"[\ H (9)
This equation had been further corrected by Proano et al. in 1989 [2.5]. It is found that the behavior of carrier mobility under low gate bias can be expressed more correctly by using the flat-band voltage VFB instead of the threshold voltage VTH. The
flat-band voltage VFB is defined as the gate voltage at minimum leakage current occur.
Furthermore, Levinson assumed that the channel thickness was constant and equal to the thickness of poly-Si film tpoly-Si. This simplifying assumption is permissible only
for very thin film (t<10nm), which is not applicable to common thickness for poly-Si TFTs. A better approximation for channel thickness tch in an undoped poly-Si film is
given by defining the channel thickness as the thickness at which 80% of the total charge resides. Therefore, by solving the Poisson’s equation, the channel thickness is given by
]^_ WX `YZY0J
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Substituting above modificatory terms into the (2-9), and the ID current of poly-Si
TFTs can be expressed as BAD*5F G cd MNO e PTRSTfY0J Y Z g ;0JT"-/"ab Th (11)
According to equation (2-11), we can extract the trap state density (Nt) from the
slope of the curve ln[ID/(VG-VFB)] versus (VG-VFB)-2. The effective grain boundary
trap state density Nt can be determined from the square root of the slope
i=94j ;0J
![Fig. 3. The plots of ln [I D /(V G – V FB )] versus 1/(V G – V FB ) 2 curves at V D = –0.1 V and high V G](https://thumb-ap.123doks.com/thumbv2/9libinfo/8230432.170887/59.892.164.741.152.1098/fig-plots-fb-versus-fb-curves-high-g.webp)
