For an input-slew-violation pin p, we first calculate its equivalent OALg by the method described in Section II-B, where g’s output directly connects to p. Then the slew-violation problem at input pin p is transferred to an equivalent loading-violation problem at
gate g’s output. The gate g is referred to the violation gate and the net driven by g is referred to the violation net. We first apply the ESB buffer-insertion scheme to minimize the number of spare cells used to solve this loading-violation problem. The more spare cells can be saved, the larger ECO size can be implemented in the next generation of ECO. From our experience, a product could have more than 10 generations of ECO due to either large market requests or poor design.
In reality, most slew violations result from high-fanout nets. To save the spare buffers in use, we try to use one buffer to drive as many terminal pins as possible. Therefore, we need an effective grouping method to select the nearby terminal pins which can be driven by a common buffer under the loading or slew-transferred constraint. Figure 4 shows an example of a 3-terminal violation net. If we group two geometrically separated pins, such as t2 and t3 in Figure 4(b), one buffer is not enough to drive both of t2 and t3 since their wire loading is too large. However, if we group two nearby pins, such as t1 and t2 in Figure 4(c), one buffer is enough to drive both of t1 and t2.
14
Fig. 4. Example of inserted buffers for different pin grouping.
Figure 5 shows the flow of the ESB scheme. In step A, a minimum-chain algorithm is applied to obtain an order of terminal pins for the violation net, named MC order (detailed in Section IV-B). This MC order can guide the grouping of nearby terminal pins in step B
(detailed in Section IV-B). Step C calculates the ideal location of the inserted buffer based on the grouped terminal pins (detailed in Section IV-C). In step D, we attempt to map a real spare buffer closest to the ideal location while satisfying the slew-transferred loading constraint (detailed in Section IV-D). After a real spare buffer is successfully inserted, we update the violation net and recalculate the MC order of its terminal pins in step E. We repeat step B to step E until the output loading of the violation gate meets the slew-transferred loading constraint. An overall algorithm is provided in Section IV-E. We also discuss how to relax the searching criteria when no suitable buffer c an be found to solve the violation in Section IV-F.
Section IV-G describes how to handle hard macros in the ESB scheme.
15
Fig. 5. Flow of ESB buffer-insertion scheme.
The ECT buffer-insertion scheme is applied after ESB scheme. The objective of ECT scheme is to eliminate the timing violations resulted from using ESB scheme. The flow of ECT is similar to the ESB scheme except the grouping method in step B. The details are described in Section IV-H.
A. Obtain Minimum-Chain Order of Terminal Pins
As the example in Figure 4 shows, we hope to group the terminal pins of the violation net not only in the same geometrical neighborhood but also in the same direction toward the violation gate. Otherwise the wire loading to drive the grouped pins may be too large. In order to obtain such grouping, we modified a minimum-chain algorithm in [16] to get the MC order of terminal pins. The concept of this minimum-chain algorithm is to assign the closest pin as the next ordered pin each time, starting from the violation gate g (the order of g is 0).
By connecting the terminal pins one by one with such order, their total wire length can approach to minimal. This property also implies that the terminal pins with adjacent MC order are more likely in the same direction toward the violation gates as well. Figure 6 lists
16
this minimum-chain algorithm.
B. Group Terminal Pins Using MC Order
In step B, terminal pins of the violation net are first grouped assuming a type-t buffer b is used. We start from the buffer type with the highest driving capability to the one with the lowest. Then, we follow the MC order to serially add the terminal pins into the group p list.
The objective here is to obtain a group of pins p list such that the output loading of b for driving all grouped pins in p list is close to but not exceed the OALb. We estimate this output loading of b for driving p list (denoted as GOLb(p_list)) by the following equation:
(4)
Fig. 6. Minimum Chain algorithm
where n is the size of p list, pi is the ith ordered pin in p list, InCpi is the input capacitance of pi, WL(pi, pi−1) is defined in Equation 3, and WL(p1, p0) is equal to 0.
In this estimation, we assume that the terminal pins are piece-wise connected one by one.
However, the real routing of a net generated by commercial tools is like a Steiner tree, where
17
multiple terminal pins may share one common wire. Therefore, this estimation is actually an upper bound, implying that the inserted buffer by ESB scheme can safely meet the loading constraint.
C. Calculate Ideal Buffer Location
We follow the following two rules when deciding the ideal location of the type-t buffer to drive all terminal pins in p list:
R1 Use all buffer’s driving capability under the given constraint.
R2 Locate the inserted buffer as close to the violation output as possible.
To achieve R1, we first calculate the output remained load of the buffer b, denoted as ORLb, using the equation:
(5) The amount of ORLb determines the affordable wire length connecting from inserted buffer b to the last-ordered pin pn in p_list. The higher ORLb, the longer wire length can be allowed between b and pn. Thus, the ideal location of the inserted buffer b must satisfy the following equation:
(6) where Xa and Ya represents the X-axis and Y-axis coordinates of pin (or gate) a, respectively. To make the buffer b closer to the source pin g, we limit the ideal location of b on the straight line between g and pn. Then we add another equation:
(7)
18
Last, we can obtain the ideal location of b by solving both Equations 6 and 7, assuming the equality holds in Equations 6.
D. Search Real Spare Gate
We first use the Manhattan distance between the last-ordered pin pn and the ideal buffer location as the radius to draw a diamond-shape region centered at pn. The buffer found in this diamond-shape region can satisfy Equations 6. To make the buffer closer to the violation gate g, we use the same radius to draw another diamond-shape region centered at the ideal buffer location. We then attempt to select the buffers locating in the intersection of the two regions.
This searching can make sure that the selected buffer, if any, is on the way toward the violation gate g, which helps to achieve R2. Figure 7 shows an example of these two diamond-shape regions.
Finally, we select the type-t buffer closest to the ideal location in the intersection region. If such type buffer cannot be found in the intersection region, then we change the buffer type to one with lower driving capability and repeat step B to step D.
19
Fig. 7. Search buffer in the ORL diamond shape
E. Overall Algorithm of ESB Scheme
Figure 8 details the general algorithm of ESB scheme. In this algorithm, Line 6 to 17
corresponds to step B in Section IV-B. Line 18 corresponds to step C in Section IV-C. Line 19 to 20 corresponds to step D in Section IV-D.
Figure 9 illustrates the process of inserting buffers onto a 6-terminal violation net. In Figure 9(a), the labeled number on each terminal represents its MC order. We first group the
farthest pins in G1 (5 and 6) according to step B. In Figure 9(b) a spare buffer is inserted to share the loading of grouped pins through step C and D. Pin 5 and 6 are hence removed from the violation net. Assume OALg is still less than GOLg (mc list) in this case, we need to
recalculate the MC order for the updated violation net with 5 terminal pins. Then we repeat the step B, C, and D to group terminal pins in Figure 9(c) and insert another buffer for the grouped pins in Figure 9(d). After that, OALg become less than GOLg (mc list). So total two buffers are inserted to solve the violation. Figure 9(e) shows the final result.
20
F. Background Tolerance
In order to drive as many terminal pins as possible, we keep on adding terminal pins into the grouping list p list as long as GOLb(p_list) is less than OALb. A larger GOLb(p_list) will result in a smaller ORLb (as defined in Equation 5) and, in turn, a smaller radius of the two diamond-shape regions. This radius reduction may shrink the searching space of candidate spare buffers, such as the situation in Figure 10(a). Therefore, when no candidate spare buffer can be found to drive the pins in p list, we may remove the last-ordered pin in p list to increase ORLb. Then we restart the searching for candidate spare buffers, such as the situation in Figure 10(b).
G. Detour Insertion to Avoid Hand Macro
In seldom cases, the violation net contains terminal pins locating on the opposite two sides of a hard macro such as Figure 11(a). The predicted location of the inserted buffer may be inside the hard macro such as Figure 11(b). To avoid this situation, MOESS need record the area of hard macros in advance. Once the predicted buffer region is located in hard macro’s area, we perform a detour search along the boundary of the hard macro to find a proper buffer such as Figure 11(c). In such a case, the search could be from either direction of the source pin. In MOESS, we start from the direction which can form a shorter detour path to the target pin.
H. ECT Buffer-Insertion Scheme
ESB scheme focuses on using a buffer to support as many terminal pins as possible.
21
Although the slew or loading violation can be solved by ESB scheme, the delay of some paths may exceed the timing constraint due to the extra gate delay of inserted buffers. This case usually occurs when a new-added function is connected to a timing-critical net. After studying those timing-violation cases, we found that most violations result from the sharing of a
common buffer between a timing-critical path and long new-added wires, such as the case in Figure 12(a). The labeled number for each pin represents its Manhattan distance to the source pin of the violation net. Those new-added wires can be designed as multi-cycle paths to meet the timing constraint but the original paths cannot.
Fig. 8. MC buffer insertion algorithm
22
Fig. 9. An example process of ESB buffer-insertion scheme.
To avoid such cases, ECT buffer-insertion scheme will separate the grouping of long-wire terminal pins from the others. So the terminal pins on critical paths need not to share a
common buffer with other long-wire terminal pins, such as the case in Figure 12(b). Therefore, ECT scheme basically follows the same flow of ESB scheme but change the step of terminal-pin grouterminal-ping (step B). In ECT scheme, a terminal terminal-pin whose Manhattan distance to the source pin exceeds a threshold is defined as the wire terminal pins. Then, for only those long-wire terminal pins, we determine the pin grouping using the same procedure described in Section IV-B and insert buffers accordingly. After that, the same procedure is applied to the other terminal pins again. As a result, the number of inserted buffer may be increased while the propagation delay for critical paths can be reduced.
Fig. 10. Spare buffers in the intersection before (a) and after (b) backward tolerance.
23
Fig. 11. (a) spare empty area(placement/routing obstacle) (b) spare gate search failed (c) detour insertion
The threshold of the Manhattan distance to the source pin is actually a parameter in ECT scheme. ECT scheme will try different thresholds within an empirical range to check if the timing violation can be solved. If not, ECT scheme will report the case with the best negative slack.
24