Here we address the effect of drain bias on the measurement results. The measurements were carried out for n-channel operation by sweeping gate voltages from –3 to +6V, and for p-channel operation by sweeping gate voltages from –1 to –10 V, with drain voltages |VDS|= 0.1V or 5V, and sub-gate voltage |Vsub|=50V.
Figure 3.7 shows the characteristics of the ID-VG for the FID SB-TFT with CoSi2 S/D material. The channel film is SPC poly-Si film. As can be seen in the figure, the on-current in n-channel operation is more sensitive to VDS than p-channel operation, owing to the higher barrier height of electrons than holes at the CoSi2/Si contact. The extracted DOS results are shown in Fig. 3.8. It is observed that the DOS remains
unaffected in the mid-gap regime, but increases significantly near the band edge when
|VDS| is set at 0.1V, especially for the conduction band edge. It was shown previously that the increase in |VDS| could decrease the source-side carrier tunneling distance [12]-[14], and thus the parasitic resistance. As the Fermi level moves toward the band edge, the operation is near threshold and becomes more sensitive to the contact resistance. As a result, the DOS is overestimated when |VDS| is not sufficiently high.
3.3 Effects of the channel length
Figures 3.9~3.12 shows the ambipolar transfer characteristics and correspondingly extracted DOS for four devices with self-aligned spacer and channel length ranging from 0.8 to 5 µm. The on-current measured at |VDS| = 0.1 V as a function of channel length for these devices is shown in Fig. 3.13. The on current
becomes larger as the channel length becomes shorter due to reduced channel resistance. However, the n-mode current is almost independent of channel length when channel length is lager than 1 µm, indicating the significance of contact resistance due to larger electron barrier height. In these measurements, the mid-gap DOS is almost the same (about 1.2x1018 eV-1cm-3), while the tail DOS is strongly dependent of the applied bias conditions. Figure 3.14 (a) & (b) compare the DOS results among devices with different channel length and |VDS| of 5 V. It can be seen
that reasonable agreement is achieved among these devices, indicating that |V
DS| of 5 V is sufficient large so the effects of parasitic resistance is insignificant.
3.4 Effects of drain-side extension length
Figure 3.15 (a) shows the ambipolar transfer characteristics of device with self-aligned and non-self-aligned (XD = 3 µm) FID length under |VDS| of 0.1V. The extracted DOS results are shown in Fig.3.15 (b). It can be seen that the on-state current is significantly lower for device with XD of 3μm. This is apparently due to the larger parasitic resistance in the FID region and thus leads to an overestimation of tail DOS, as shown in Fig.3.15 (b). Such disparity can, again, be removed by increasing the |VDS| to 5 V, as shown in Fig.3.16.
3.5 Effects of measurement temperature
Figure 3.17 shows that the ambipolar transfer characteristics of a device characterized at 25oC and 55oC. The on-state current is larger at 55oC than 25oC, owing to the enhanced conduction of thermionic emission at higher temperature. The extracted DOS results are shown in Fig.3.18. We can see that the results are in reasonable agreement with each other, indicating that the zero-temperature
approximation mentioned in Chap. 2 stands in the characterized temperature range.
3.6 Results comparison with conventional approach
Figure 3.19 shows and compares the DOS results extracted by performing the characterization process on a FID SB-TFT and two conventional TFTs (i.e., p- and n-channel TFTs with degenerately doped S/D) with same channel material, which is as-deposited poly-Si films. It can be seen that results are similar which validates the DOS data deduced from the FID SB-TFT structure, even though only a single device is used in our proposed methodology.
3.7 Effects of channel crystallization treatment
The electrical performance of poly-Si TFTs strongly depends on the quality of the polysilicon film. Methods such as direct deposition of polysilicon film by low-pressure chemical vapor deposition (as-deposited poly-Si), low-temperature solid phase crystallization (SPC) of amorphous silicon, and excimer laser annealing (ELA) crystallization methods, have been carried out in this work to examine their crystallinity and its consequence on the DOS characteristics. Fig.3.20 shows the DOS extracted from samples with SPC and as-deposited poly-Si channels. Both samples received 1-hour NH3 plasma treatment. It is seen that the SPC channel shows less DOS than the as-deposited poly-Si counterparts. This is primary due to the larger grain size of SPC sample than that of as-deposited poly-Si, as characterized by the transmission electron microscopy (TEM) results shown in Fig.3.21. From both electrical and physical characterization confirm that the SPC film indeed has larger grain size and better quality than the as-deposited poly-Si film.
Figure 3.22 shows the DOS comparison between the ELA and SPC samples The results indicates that the ELA treatment could further reduced the DOS. Figure
3.23(a) and (b) show the TEM micrographs of the SPC and ELA samples, respectively.
We can clearly see that the grain size of ELA film much larger than that of SPC film, and resulting in the reduced DOS shown in Fig.3.23.
3.8 Effects of plasma hydrogenation
It was shown previously that deep trap states located near the mid gap mainly arise from dangling bond defects (predominated situated in grain boundary regions) whereas tail states may arise from distorted bond defects (predominated inside the grains) [18]. These traps could be effectively reduced after performing a hydrogenation treatment on the fabricated devices. Moreover, the relative passivation efficiencies on different types of defects can be determined and compared by comparing the DOS before and after hydrogenation. Fig.3.24 shows and compares the ambipolar transfer characteristics of the SPC samples before and after 1 hour NH3
plasma treatment. After plasma treatment, the on current is increased while the subthreshold swing is improved. The corresponding DOS results are shown in Fig.3.25. As can be seen in the figure, a hump appears near mid-gap before hydrogenation, presumably caused by the dangling bonds situated in grain boundaries.
Hydrogenation reduces in the mid-gap state density by one order of magnitude (from 1019 to 1018 eV-1cm-3). This results in improved subthreshold swing and on current. It can also be seen that, although the mid-gap state density is reduced dramatically after plasma hydrogenation, the tail state density near both valence and conduction band edges are only affected slightly. This indicates that the plasma treatment passivates the dangling bond more effectively. It may need more time to reduce the tail state density, as pointed out in Ref.18.
Figure 3.26 shows and compares the DOS of devices with as-deposited poly-Si
channel before and after plasma hydrogenation. Similarly, the DOS is reduced, though the improvement on tail states seems to be more significant, as comparing to the SPC case shown in Fig. 3.25. This phenomenon is not fully understood at this stage and maybe presumably be related to the column grain texture with the smaller grain size.
Table.2 lists DOS of the devices before and after plasma hydrogenation.
3.9 Effects of silicide material
Figure 3.27 shows the ambipolar transfer characteristics of FID SB-TFT device with PtSi Source/Drain. We can see that the on current is larger in p-channel operation than in n-channel operation. This is due to the lower barrier height for holes (~0.24eV) than for electrons (~0.88eV) in the case of the PtSi/Si contact. As a result the contact resistance will be significant for n-channel operation. The extracted DOS is shown in Fig.3.28 together with that obtained from the device with CoSi2 S/D. We can see that the upper-band DOS is obviously overestimated for device with PtSi S/D, owing to the high parasitic resistance presenting at the silicide junction. Thus, for full-band gap DOS analysis, it is essential to choose the mid-gap silicide material to obtain accurate gap state density distribution.
3.10 Analysis of full band-gap DOS in SB poly-Si FinFET
Recently, our group proposed poly-Si SB-TFT with nano-scale channel width featuring silicided Schottky barrier source/drain with field-induced source/drain extension. This device is also called poly-Si SB FinFET. The process flow of fabricating these nano-scale devices is similar to that of fabricating conventional structures except three notable differences: First, e-beam lithography was employed for device patterning throughout the fabrication. Secondly, the etching selectivity of
poly-Si to SiO2 must be high enough to ensure that the poly-Si channel is not damaged during the process. The etching selectivity in both main etch and over etch steps are larger than 100, which is suitable for nano-scale gate patterning with ultra-thin gate dielectric layer. Thirdly, 10nm-thick sacrificial oxide is needed to remove the damage created by dry-etching processes on the sidewall surface of the poly-Si fin.
In this section we characterize and examine the DOS of the poly-Si SB FinFET.
Two splits of samples, denoted as SA- and NSA-series, were characterized. The top view of the SA-series devices with 15nm offset length is shown in Fig. 3.29(a). This device employs a self-aligned sidewall spacer to define the offset region. The top and side views of the NSA-series devices with 1µm offset length in both drain and source sides (XD and XS) are shown in Figs. 3.29(b) ~ (d). An extra mask was employed to define the 1µm offset channel region. It is worth noting that these devices actually have a triple-gate structure, as can be seen in Fig. 3.29(d) which shows the cross-sectional view along the B---B’ direction in Fig 3.29 (b). As a result, the effective channel width should be the sum of the Si Fin width (50nm) plus twice of the Si thickness (50nm).
Figure 3.30 shows the ambipolar transfer characteristics of FinFET structure at sub-gate voltage Vsub=2V and 5V. The on-state current increases as the sub-gate voltage increases. To explain this trend, Fig.3.31 shows the band diagram near source side. As the sub-gate bias increases, the source-side field emission current is enhanced by the narrowed tunneling width and therefore higher on-current. Fig.3.32 and Fig.3.33 show the ambipolar transfer characteristics of different channel width. The device with a wide (i.e., 5um) channel width serves as the “de facto” planar structure.
While the other nanoscale device with three fins, each fin having a width of 50 nm and height of 50 nm, represents an effective channel width of 450 nm. We can see that
the poly-Si SB FinFET exhibits much steeper subthreshold swing as comparing to the device with planer with. Fig.3.35 shows the ambipolar transfer characteristics and Tx(d(logG)/dVG) against 1000/T, from which we can deduce that the flat band is around –0.4V. Fig.3.35 shows the extracted DOS of the planar structure (W=5um) and FinFET (W=0.45um) structure. It can be seen the DOS is smaller in the FinFET structure than in the planar structure. This is because the FinFET has a channel thickness that is narrower than the depletion length and thus the effective DOS within the channel is lowered. In other words, the controllability of gate bias on adjusting the channel potential is promoted when a nano-scale fin channel is employed, and thus the subthreshold swing is improved.
3.11 A New & Simpler Methodology to Determine Flat-Band Voltage
Precisely determine the flat-band voltage is essential for building the relationship between DOS and the energy level inside the gap. As mentioned above, in order to achieve this purpose, a number of measurements of the conductance need to be performed at various temperatures. Moreover, in conventional approach, the process should be conducted separately on p- and n-channel devices. It is thus very tedious and time-consuming. In this work, we experimentally found that the flat-band voltage obtained using the above method is actually very close to the gate voltage at the intersection point of p- and n-mode I-V curves measured at room temperature. An example is provided by the results shown in Figs.3.1 and 3.3. We can see that the p- and n-mode I-V curves at 25 oC intersected at VG ~ -2V, which is very close to the result obtained in Fig.3.1 (VFB ~ -2.1 V). We thus propose a way and simpler to determine the flat-band voltage by simply measuring the gate voltage at the
intersection point of p- and n-mode I-V curves measured at room temperature using a SB TFT. To validate this method, a number of samples were characterized and the results are summarized in Fig.3.36. We can see that the difference between the conventional method and our method is indeed small. To take advantage of this simpler method, we modify the flow chart for analysis of full band-gap DOS using the SB TFT in Fig.3.37. This scheme greatly simplify the process of conventional approach shown in Fig.2.2, since only two I-V measurements performed at room temperature on a single device performed at room temperature is required for the analysis.
Chapter 4
Conclusions and Future Work
4.1 Conclusions
In this work, we have proposed and successfully demonstrated a novel approach to obtain the full band-gap DOS in the channel of TFT devices. In this approach, the field-effect conductance method is performed on an SB poly-Si TFT which has the capability of ambipolar operation. Both incremental and temperature methods are adopted on the SB and conventional devices to construct the relationship between DOS and the energy level in the gap. For devices with the same channel material, the results are in good agreement among the different measurement schemes, indicating that the novel approach is very reliable.
We have also characterized the dependence of both electrical and structural parameters on the measurement results in order to set suitable test conditions. Our results indicate that the parasitic resistance presenting in the channel would result in an overestimation of tail state density. Accurate DOS extraction can be obtained by employing sufficiently high drain and sub-gate biases and short electrical junction. In addition, near-mid-gap silicide material such as CoSi2 is desirable for reliable full band-gap DOS analysis.
We have also characterized the effect of process treatments including re-crystallization and plasma hydrogenation steps on the DOS characteristics. Their impacts could be clearly identified using the new approach. Benefits of using a nano-scale Fin channel for promotion of the controllability of gate voltage over the channel potential is also clearly demonstrated.
Finally, we show that the flat-band voltage could be obtained by simply measuring the gate voltage at the intersection point of p- and n-mode I-V curves. The overall process is thus greatly simplified and cost-saving compared to conventional approach, since only two I-V measurements performed on a single device at room temperature are all that are needed. We strongly believe that the novel method is extremely useful for practical applications.
4.2 Future Work
Since our method provides a simple and efficient way to map the full band-gap density of states of the channel material, it will be a very powerful tool in the development and production of thim film transistors. We believe our method could be applied to TFT technologies using poly-SiGe or organic channel materials. The method would be efficient in understanding the impact of process treatment on the device characteristics and on addressing some material issues such as the impurity contamination and segregation in the channel. With specially designed test structures, the method may also be useful to characterizing the reliability issues of TFT devices such as the hot-carrier induced damage effects.
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