Emerging NVM Technologies

In addition to PCM, NVM Duet is applicable to main memory made of other emerging NVM technologies, including memristor and STT-RAM [77, 81]. Certain modifications are required because of the different data storage mechanisms and data retention mecha-nisms among these NVM technologies as discussed as follows.

NVM Duet can be applicable to memristor-based main memory with moderate mod-ifications because memristors share many key characteristics with PCM. Memristors use metal oxides as their active material to store data. By electrically moving the boundary of doped and undoped regions of metal oxides, a memristor cell can exhibit different resis-tances to represent different data. Duet Scheduler can be directly applied to memristor-based main memory because Duet Scheduler involves little device-level properties. Dual Retention is also applicable because memristors also allow run-time tradeoffs between write speed and retention capability [55]. Smart Refresh is also applicable because sim-ilar to PCM, the resistance of a memristor cell gradually changes over time after the cell is written, and the remaining retention capability of a memristor cell can thus be inferred based on the resistance. One required modification is that the retention capability and re-freshing interval for working memory should be re-calculated (e.g., based on the analytic models presented in Section 4.4.2).

Compared with memristor-based main memory, a bit more modifications are required before STT-RAM-based main memory can adopt NVM Duet. STT-RAM uses magnetic tunnel junction (MTJ) as its active material. An MTJ element combines two ferromag-netic layers, a free layer and a fixed layer. The magnetization direction of the free layer can be electrically flipped relative to the fixed layer to represent one bit of information.

Duet Scheduler is directly applicable to STT-RAM-based main memory, while Dual Re-tention is not because STT-RAM requires MTJ sizing to exploit the tradeoffs between write speed and retention capability: a smaller MTJ volume exhibits shorter write latency but a higher probability of being randomly flipped (i.e., lower expected retention capa-bility). Without run-time retention adjustability, physically partitioning STT-RAM space into working memory and persistent store is required for Dual Retention. Interestingly, Smart Refresh is applicable to STT-RAM. The retention capability of an MTJ corresponds to a period from the time the MTJ is known correct (e.g., right when the MTJ is written) until the time the MTJ is considered unreliable, i.e., the risk that a random flip has oc-curred during the period is unacceptably high. Therefore, as long as an STT-RAM cell

is known correct during the read stage of a refresh operation, the cell can skip the write stage of the refresh operation while keeping reliable until the next refresh operation.

4.6 Related Work

Several previous studies have proposed using PCM as working memory [82, 131, 172].

Limited write endurance and relatively poor write performance are the two major con-cerns for PCM-based working memory. To address the write-endurance issue, differential write [82, 131, 172] eliminates unnecessary writes to PCM. Wear leveling [129, 130, 138, 172] spreads the writes across the entire PCM space to avoid concentrated memory wear.

Error correction schemes [16, 45, 63, 126, 137, 139, 165] keep the PCM functional even if certain cells wear out. To address PCM’s write-performance issue, write cancellation and write pausing [128] allow critical reads to abort or pause on-going writes. Write trunca-tion [70] exploits the error-correcting code’s ability to curtail a write operatrunca-tion before all of the bits are written correctly. In [127,167], PCM asymmetries are exploited to improve write performance. In [35, 57, 69], bit flipping and power budgeting are used to maximize PCM’s write parallelism, given a limited chip power supply.

PCM is also considered to be a promising solution for building high-performance persistent store. Because of the differences between PCM and traditional block-based storage in terms of access speed and access granularities, significant efforts in innovative programming models and system architecture design are ongoing [26, 28, 39, 40, 107, 108, 153–155, 157]. For example, BPFS [40] incorporates a new file system and hardware architecture. NV-heaps [39] and Mnemosyne [155] propose languages and libraries that enable in-memory persistence. In [107,108], memory allocation, memory protection, and cache architecture tailored to NVM-based persistent store are proposed.

Unification of working memory and persistent store in NVM was envisioned in [17, 29,132]. Based on a unified architecture, [116] integrates the space management of work-ing memory and persistent store. This approach maximizes the available workwork-ing mem-ory and reduces page swapping. Memorage [72] performs global wear leveling between working memory and persistent store to maximize the achievable lifetime.

Prior studies have presented Retention Relaxation for NVM to optimize the write performance or write endurance of NVM systems. In particular, these studies target STT-RAM caches [71, 114, 146, 148] and NAND flash SSDs [25, 96, 97, 105, 117], and refresh-ing is adopted. For PCM, selected patent applications [56,100,121] also present refreshrefresh-ing the PCM but do not focus on trading off retention capability and write performance in the manner emphasized by Retention Relaxation. Several papers [14, 15, 140, 164] also ana-lyze PCM’s retention capability and refreshing overhead, but they assume a pure working memory architecture instead of a unified structure, as in this work, and their analyses are based on PCM with a uniform target-band allocation. The work in [140] proposes lower-ing the PCM’s information density in return for enlarglower-ing the target bands and improvlower-ing the write speed. Shen’s master’s thesis [141] studies Retention Relaxation for improving PCM’s write speed, which is closely related to the Dual-Retention PCM portion presented in this chapter. Concurrent with this work, Approximate Storage [135] relaxes the error rate guarantee for data that are error-tolerable. Similar to the Dual-Retention PCM, Ap-proximate Storage manipulates PCM’s target bands for improved write speed.

4.7 Summary

In this chapter we present a novel unified working memory and persistent store architec-ture, NVM Duet. We observe that naively making NVM serve as both working memory and persistent store is a suboptimal approach because of the intrinsic differences between the two use cases. This problem occurs because without knowledge of the use case of an individual request, a unified memory architecture must serve all requests under the highest design constraints in terms of consistency and durability.

NVM Duet adopts a cross-layer approach to provide the required consistency and durability guarantees for persistent store while relaxing these constraints if accesses to NVM are for working memory, thereby improving system performance. Specifically, a new HW/SW interface allows the OS to convey the use case of data declared by the programmer (working memory or persistent store) to the memory controller. The mem-ory controller is then enhanced with a new scheduler, Duet Scheduler, which seeks to

fully exploit the parallelism present in the address stream while respecting the write order to guarantee the consistency of persistent store. Furthermore, a new PCM architecture, Dual-Retention PCM, is proposed to provide two retention levels and relax the durability constraint for working memory. To make Dual-Retention PCM appealing for practical adoption, NVM Duet employs Smart Refresh that exploits PCM devices’ property to eliminate unnecessary refresh overhead. Experiments based on full-system simulations and workload mixes of persistent and conventional workloads demonstrate that our NVM Duet design achieves up to a 1.68× (1.32× on average) speedup over the baseline.

Chapter 5

Conclusions and Future Directions

With the ever-increasing demands to support emerging applications such as cloud com-puting, social networking, and big data analytics, it has never been more important to design and build low-power, high-performance servers. To achieve this goal, flash-based storage, flash-based storage caches, and PCM-based main memory are key enabling tech-niques. Both industry and academia dedicate increasing efforts to investigate design and optimization for the adoption of these techniques in servers.

Over the course of this dissertation, I identified new insights and opened up new design and optimization space for NVM in servers. Specifically, different from many prior flash-related studies that have focused on file systems, I/O schedulers, and FTL, I especially considered the increasingly significant device-level characteristics of flash and propose co-designing hardware and software layers collaboratively. Moreover, most prior PCM-related studies have focused on architecting PCM as either pure working memory or pure persistent store, whereas I focused on revisiting and redesigning hardware and software layers so that PCM can efficiently serve as both roles.

In Chapter 2, I presented Retention Relaxation, the first work on optimizing flash storage by relaxing flash’s data retention capability. I developed a flash model to evaluate the benefits if flash’s multi-year retention capability can be reduced. I also demonstrated that in real systems, write requests usually require days or even shorter retention. I de-signed flash storage which handles host writes with shortened retention while handling background writes as usual to optimize the write speed and ECC cost-performance. I also

presented corresponding retention tracking schemes to guarantee that no data loss hap-pens due to a shortage of retention capability. Simulation results demonstrated that the proposed design achieves 1.8–5.7× write response time speedup. I also showed that for future flash storage, Retention Relaxation can achieve a superior cost-performance point for the ECC architectures.

In Chapter 3, I presented DuraCache to tackle the lifetime issue of flash caches in dat-acenters. DuraCache exploits the fact that flash caches are write-through caches. There-fore, uncorrectable errors in flash caches can be handled like cache misses which bring in correct data from HDD arrays. In addition, DuraCache gradually allocates more ECC parities associated with data when flash reaches wearout thresholds. These strategies al-low flash to continue operating with slightly increased miss rates and gradually sacrificed available capacity. I conducted empirical experiments characterizing the correlation be-tween flash’s BER and write cycles and demonstrated that DuraCache enables flash caches made of MLC flash to achieve a 4.1 years of service life assuming a TPC-C workload.

In Chapter 4, I presented the insight that naively making PCM main memory simul-taneously serve as working memory and persistent store is suboptimal. Persistent store demands consistency and durability guarantees, thereby imposing additional design con-straints on the memory system. Consistency is achieved at the expense of serializing multiple write requests. Durability requires memory cells to guarantee non-volatility and thus reduces the write speed. I presented NVM Duet, a novel PCM main memory archi-tecture, which provides the required consistency and durability guarantees for persistent store while relaxing these constraints if access to NVM is for working memory. Sim-ulation results demonstrated that NVM Duet achieves up to 1.68× (1.32× on average) speedup compared with the baseline design.

There are several extensions that I would like to pursue in the future:

1. One future research direction is to analyze the proposed architectures using real systems and real applications. I plan to utilize DRAM-based FPGA platforms to emulate servers adopting PCM main memory with NVM Duet. I also plan to pro-totype flash-based storage that adopts DuraCache and Retention Relaxation. Based

on real systems, I can investigate the design space and optimization opportunities of executing emerging applications on NVM-enabled servers. More architectural insights into adopting NVM in servers are also expected to be made.

2. The proposed architectures can be extended considering different NVM technolo-gies. NVM Duet is designed and evaluated using PCM as the target memory tech-nology though, the concept is applicable to other NVM technologies such as mem-ristors and STT-RAM [77, 81]. Similarly, the ideas of DuraCache and Retention Relaxation are also potentially applicable to improving the lifetime and perfor-mance of PCM-based storage [26]. Additional modeling techniques and optimiza-tion methodologies are anticipated to be developed for investigating these extended directions.

3. The proposed architectures can be collaboratively combined with one another. For example, in the future a server can equip both PCM main memory and flash caches, and it will be natural and reasonable to simultaneously adopt both NVM Duet and DuraCache architectures in one system. Therefore, evaluating and optimizing the interplay among NVM Duet and DuraCache for this type of combination are inter-esting future research topics.

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