Access frequency is a characteristic usually considered in flash storage optimization. Dy-namic data clustering [34] groups data with similar write frequency together to increase flash storage’s cleaning efficiency. SieveStore [124] exploits the skewness of storage ac-cess frequency in datacenters to improve the effectiveness of flash caches. In comparison to access frequency considered in these studies, we focus on the time interval between two successive writes to the same address, which defines the retention requirement.
Several works propose device-aware optimization schemes for flash storage. The variation-aware FTL [52] exploits the differences of page write speed in multi-level cell (MLC) flash to improve flash storage’s responsiveness. The dynamic codeword transi-tion ECC [150] improves ECC capability by adapting the ECC codeword size to the P/E cycles of flash. In [158], write speed is improved by enlarging the step size of ISPP, compressing user data, and employing stronger ECCs. In [118], write speed and defect tolerance are improved by exploiting the wearout dynamics of flash. In [106, 156], the recovery phenomenon in flash is exploited to improve flash storage’s lifetime. In com-parison to these studies, our study considers the retention requirements of workloads and relaxes flash’s retention to optimize flash storage. Our design is generally orthogonal to the above device-aware optimization.
Some related studies [146, 148] propose relaxing the non-volatility of CPU caches made of spin-transfer torque (STT)-RAM to improve the energy and latency of CPU caches. Their schemes require downsizing STT-RAM cells at the manufacturing time. In comparison, we focus on storage systems made of flash. Our study breaks the traditional design constraint that storage systems need to retain data for a long time, e.g., a year.
Moreover, our design involves no manufacturing-time cell sizing and thus exhibits run-time flexibility to adjust flash’s non-volatility.
2.8 Summary
We present the first work on optimizing flash storage by relaxing flash’s retention capa-bility. We develop a flash model to evaluate the benefits if flash’s year-long retention requirement can be relaxed. We demonstrate that in many real systems, write requests usually require days or even shorter retention. To optimize the write speed and ECC cost-performance, we design flash storage which handles host writes with shortened retention while handling background writes with normal retention. We present associated retention tracking schemes to guarantee that no data loss happens due to a shortage of retention capability. Simulation results demonstrate that Retention Relaxation achieves 1.8–5.7×
speedup in write response time. We also show that Retention Relaxation can achieve a superior cost-performance point for the ECC architectures of future flash storage.
Chapter 3 DuraCache
3.1 Introduction
Flash has gained popularity in datacenter storage. Although it is still controversial whether flash can ultimately replace HDDs, it has been widely accepted that utilizing flash as stor-age caches (i.e., flash caches) is a cost-effective solution for optimizing storstor-age perfor-mance. Major storage vendors, such as EMC, Fusion-io, and NetApp, all have announced their flash cache solutions [42, 47, 113].
Flash caches can be deployed in both host servers and storage servers. One bene-fit of equipping servers with flash caches is accelerating applications that demand high storage performance such as online transaction processing. Employing flash caches has another important benefit that the storage performance can be decoupled from the num-ber of HDD spindles. Traditional design strategies increase the numnum-ber of HDD spindles to boost the performance of a storage system. However, with single-disk capacity grow-ing much faster than the performance nowadays, addgrow-ing HDDs for performance becomes inappropriate because additional spindles mean additional power consumption, space re-quirements, cooling rere-quirements, and underutilized storage capacity. By intelligently caching frequently-used data blocks in flash caches, storage systems can deliver high per-formance without the drawbacks of HDD over-deployment.
Figure 3.1 illustrates a scenario that flash caches supplement a HDD array in a storage server in a datacenter. The storage server is responsible for communicating to the attached
Storage Server
Flash Cache
HDD Array Host Server
Hit
Miss
Hit
Storage System
Users
Datacenter
Flash Cache
Figure 3.1: Flash caches in a datacenter
HDDs and servicing I/O operations from the host server. Both the storage server and host server are equipped with a flash cache. Reads that hit the flash caches can be directly serviced by the flash caches. By doing so, a portion of I/O operations are filtered out, and hence less pressure is imposed on the HDD array, whose I/O operations per second (IOPS) is limited by the speed of head movement and platter rotation. One thing worth noting is that in a production environment, flash caches are write-through caches [42, 79, 113].
Data that are written to flash caches have a valid copy in HDD arrays as well. The write-through policy forces writes to persist in the HDD array to ensure high availability, data reliability, end-to-end data integrity, and disaster recovery.
There are two types of flash memory cells, single-level cells (SLCs) and multi-level cells (MLCs). An SLC stores one bit of information per cell, while an MLC stores multi-ple bits by dividing the threshold voltage window of a cell into multimulti-ple levels. An MLC flash cache is more appealing than an SLC one because the former can have up to ten times more capacity than the latter at the same cost [105]. This advantage comes from the fact not only that an MLC stores more bits per cell than an SLC, and equally importantly that MLC flash accounts for the majority of worldwide flash consumption and enjoys the economies of scale in manufacturing.
However, most flash cache solutions are forced to adopt SLC flash because of the insufficient endurance of MLC flash [8]. Let us take modern 25-nm two-bit MLC flash and a typical datacenter workload, TPC-C, for example. Modern 25-nm two-bit MLC flash can only sustain 3000 program and erase cycles (P/E cycles) before wearing out, and TPC-C can generate write traffic at an average rate of 39 fills per day to flash caches [8].
That means, the lifetime of MLC flash caches is only 77 days (300039 = 77). Therefore, it is critical to resolve the lifetime issue to enable the adoption of the MLC technology in flash caches.
In this chapter, we take a fresh look at designing a reliable flash cache. The fact that flash serves as caches instead of storage leads to different design philosophies to tackle the lifetime issue. First, unlike flash storage in which raw errors of flash must be corrected using the built-in ECC mechanism, raw errors that are uncorrectable in flash caches can be recovered by accessing HDD arrays. Second, capacity is a key specification of flash storage. A shortage or change in capacity is unacceptable to customers [5] and can cause unexpected errors in applications and OSes. In comparison to flash storage, flash caches are transparent to applications and end users. Therefore, part of the capacity can be sacrificed to increase the ECC strength and prolong the lifetime when a flash cache reaches wearout thresholds. Based on these observations, we propose DuraCache that is able to allow flash caches to be used beyond rated endurance based on two design principles: fault tolerance and graceful degradation.
Specifically, DuraCache features two mechanisms, Error Transformation and Dynamic-Rate SSD (DR-SSD), corresponding to fault tolerance and graceful degradation, respec-tively. Error Transformation converts uncorrectable errors in flash caches into cache misses, which bring in valid data from HDD arrays. Evaluation shows that Error Transfor-mation can improve the lifetime of an MLC flash cache by 1.7× at the cost of less than 1%
of cache hit loss. DR-SSD allocates more ECC parities associated with data when flash reaches wearout thresholds. This technique allows flash caches to continue operating by sacrificing cache capacity. Evaluation shows that DR-SSD can increase the lifetime of an MLC flash cache by 3.5× at the maximum expense of 11% cache capacity sacrifice.
Combining Error Transformation and Dynamic-Rate SSD enables an MLC flash cache to sustain 58k P/E cycles, i.e., 4.1 years of service life assuming a workload generating write traffic at an average rate of 39 fills per day like TPC-C [8].
The rest of this chapter is organized as follows: Section 3.2 describes background and related works. Section 3.3 describes the proposed mechanisms. Section 3.4 presents experiments evaluating the effectiveness of the proposed mechanisms. Section 3.5 sum-marizes the chapter.