Chapter 5 Experimental Results
5.6 Error-shooting
The improper layout of the taper buffer leads to the degradation of the driving capability due to too large parasitic resistance in the output. By the way, the post-simulation of the clock generator should contain the parasitic resistance extraction from the taper buffer and the PAD.
We should note that the simulation result becomes suspected once exceeding the effective operating range of the model that is offered from the foundry. Especially in the dual supply design, the interface of 3.3V and 1.8V devices may exceed the operating range and is suggested to configure as shown in Fig.5.6.1.
Fig.5.6.1 Interface of VCDL and isolation buffer.
To eliminate the body effect, the bulk of the delay cell is tied to the source. However, large current consumption of the chip is suspected to latch-up problem. Unfortunately, the latch-up phenomenon cannot be detected in the simulation.
We can prevent latch-up by layout according to the technology documents:
- Any NW without direct connection to VDD and with hot OD inside it should be surrounded by double guard ring.
Table 5.1 Performance Comparison (continued)
(Continued)
Chapter 6
Conclusions
6.1 Final Discussion
In this section, we discuss the internal co-relation as a whole for the final look of this work.
The programmable multiplication factor using previous frequency multiplication method gains 0.5X-based resolution of frequency multiplication factor and the frequency multiplication factor up to 4X in this work. Someone may try to promote the operation frequency of output clock by increasing the total number of delay stages and it seems work in this mechanism. However, the maximum operation frequency is also limited by the frequency multiplier itself whatever we increase the multiplication factor as analyzed before. Also, in increasing of delay stages degrades the jitter performance of DLL and the jitter must be estimated and controlled under an acceptable range according to their applications. The input clock range is limited by the building blocks in DLL, such as the linear range of PD, and the delay range of VCDL. The former is mainly decided by the circuit architecture, and the latter is the trade-off between delay range and noise accumulation. The settling behavior is decided by the loop bandwidth of DLL and the choice of the loop bandwidth also affects the phase noise performance, area, and power dissipation.
6.2 Epilogue and Future Work
A wide frequency operating range clock generator for dynamic frequency scaling is presented and achieves 0.5X-based frequency multiplication factors. This work is devoted to reach the compromise between the trade-off of multi-dimensional parameters, such as bandwidth, operating range, stability, noise, speed, supply voltage, etc. The dominant problem of each building block is taken into consideration and has tackled by the system analysis, circuit design techniques, and layout skills.
For low supply voltage operation in deep submicron process, the low jitter clock generator with wide frequency operating range will be more challenged. There are some suggestions for the future development. Since robustness is the best advantage of the digital circuit, all digital DLL-based clock generator with highly noise immunity and area-efficient will be the next star as long as the timing resolution can be promoted. Recently, a programmable duty cycle correction loop is a popular research topic. To combine clock generation with duty cycle adjustment can be another direction. Finally, also the most difficult issue is to generate much higher fractional-N resolution of frequency multiplication factor.
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