• 沒有找到結果。

Chapter 4 Experimental Results

4.3 Experiment 2

In experiment 2, we compare the performance of MC weight tuning algorithm working on different complexity of bus matrix architecture. As shown in Figure 29, Figure 30, and Figure 31, they all are bus matrix architectures with the different complexities of architectures. There are two buses in Figure 29, three buses in Figure 30, and four buses in Figure 31.

Those three architectures are simulated with lottery-based arbitration algorithms and MC weight tuning algorithm. If the resultant ticket assignment can make masters meet all real-time requirements and all bandwidth requirements simultaneously, it is a successful case. Otherwise, if one requirement is missed, it is a fail case. We randomly generate pattern for different bus workloads and compare the results. As shown in Table 14, the first column gives the bus workloads varying from 60% to 95%. For each set of bus workload, 100 random patterns of different required bandwidth combinations are generated. The

“2-bus” means the architecture shown in Figure 29 is used. The “3-bus” means the architecture shown in Figure 30 is used. The “4-bus” means the architecture shown in Figure 31 is used. We accumulate the numbers of successful cases of these three and show the results in Table 14.

Figure 29 : Bus matrix architecture with two buses

Figure 30 : Bus matrix architecture with three buses

Figure 31 : Bus matrix architecture with four buses

Table 14 : The number of success case under different complexity of architectures

2-bus 3-bus 4-bus

60%~65% 100 100 100

65%~70% 100 100 100

70%~75% 100 100 90

75%~80% 98 97 88

80%~85% 98 93 85

85%~90% 92 90 83

0

60%~65% 65%~70% 70%~75% 75%~80% 80%~85% 85%~90%

Figure 32 : The figure of Table 14

As shown in Figure 32, the “2-bus” (shown in Figure 29) has the best performance and it is the simplest architecture of those three. The performance of “3-bus” (shown in Figure 30) is very close to that of “2-bus”. Although the performance of “4-bus” (shown in Figure 31) is the worst of the three, the difference of results between “2-bus” and “4-bus”

is small. The MC weight tuning algorithm working on different architecture complexity results proper ticket assignment with very high successful rates.

Chapter 5

Conclusions and Future Work

5.1 Conclusions

A new weight tuning algorithm, MC weight tuning algorithm, is proposed in this thesis. It can mostly provide proper ticket assignment to lottery-based arbitration algorithms to meet real-time and bandwidth requirements simultaneously. The MC weight tuning algorithm also shows that the weight tuning algorithm cannot consider information of only one bus at one time. The weight tuning algorithm has to consider information of multiple buses. The experimental results show that the MC weight tuning algorithm working on the bus matrix architecture is better than the local-bus weight tuning algorithm working on the bus matrix architecture. Hence, the MC weight tuning is a better choice for lottery-base arbitration algorithms working on the bus matrix architecture.

As the demands of on-chip communication grow, more modern communication architectures will be proposed in the near future. If lottery-based arbitration algorithms are continually used, an efficient weight tuning algorithm is still needed as well. In the future, we intend to find a weight tuning algorithm which can be used for different communication architectures, even for different weighted or probabilistic arbitration algorithms.

Reference

[1] S. Pasricha and N. Dutt, "On-Chip Communication Architectures: System on Chip Interconnect," Morgan Kaufmann, 2008.

[2] S. Pasricha, N. Dutt, and M. Ben-Romdhane, "Constraint-Driven Bus Matrix Synthesis for MPSoC," in Asia and South Pacific Design Automation Conference, 2006, pp. 30-35.

[3] P. Sujan, G. Manfred, and M. Max, "Performance Aware On-Chip Communication Synthesis and Optimization for Shared Multi-Bus Based Architecture," in Symposium on Integrated Circuits and Systems Design, 2005, pp. 230-235.

[4] "Peripheral Interconnect Bus Architecture," http://www.omimo.be.

[5] "Virtual Socket Interface Alliance," http://www.vsi.org.

[6] "IBM Microelectronics CoreConnect Bus Architecture,"

http://www.chips.ibm.com/products/coreconnect.

[7] "AMBA 2.0 Specification," http://www.arm.com/armtech/AMBA.

[8] "Sonics Integration Architecture," http://www.sonicsinc.com.

[9] "Open Core Protocol Specification – v1.0," http://www.sonics.com, 1999.

[10] J. L. Hennessy and D. A. Patterson, "Computer Architecture: A Quantitative Approach," Morgan Kaufmann Publishers, 2002.

[11] J. L. Hennessy and D. A. Patterson, "Computer Organization and Design: The Hardware/Software Interface," Morgan Kaufmann Publishers, 2004.

[12] H. Chang, L. Cooke, M. Hunt, G. Martin, A. McNelly, and L.Todd, "Surviving the SoC Revolution," Kluwer Academic Publishers, 1999.

[13] J. Liang, S. Swaminathan, and R. Tessier, "ASOC: A Scalable, Single-Chip Communications Architecture," in International Conference on Parallel Architectures and Compilation Techniques, 2000, pp. 37-46.

[14] "ARM AMBA 3.0 Specification," http://www.arm.com.

[15] "Multi Layer AHB Specification," http://www.arm.com.

[16] C.-H. Chen, G.-W. Lee, J.-D. Huang, and J.-Y. Jou, "A Real-Time and Bandwidth Guaranteed Arbitration Algorithm for SoC Bus Communication," in Asia and South Pacific Design Automation Conference, 2006, pp. 600-605.

Integration (VLSI) Systems, vol. 14, pp. 596-608, 2006.

[18] K. Lahiri, A. Raghunathan, G. Lakshminarayana, and S. Dey, "Design of High-Performance System-on-Chips using Communication Architecture Tuners,"

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, pp. 620-636, 2004.

[19] J. Lehoczky, L. Sha, and Y. Ding, "The Rate Monotonic Scheduling Algorithm:

Exact Characterization and Average Case Behavior," IEEE Real Time Systems Symposium, pp. 201-209, 1989.

[20] C. Liu and J. Layland, "Scheduling Algorithms for Multiprogramming in a Hard Real-time Environment," Journal of the ACM, pp. 46-61, 1973.

[21] L. Sha and J. B. Goodenough, "Real-Time Scheduling Theory and Ada," IEEE Computer, vol. 23, pp. 53-62, 1990.

[22] C. A. Waldspurger and W. E. Weih, "Lottery Scheduling: Flexible Proportional-Share Resource Management," Proceeding of the First Symposium on Operating Systems Design and Implementation, pp. 1-11, 1994.

[23] Y. Zhang, "Architecture and Performance Comparison of A Statistic-Based Lottery Arbiter for Shared Bus on Chip," in Asia and South Pacific Design Automation Conference, 2004, pp. 1313-1316.

[24] B.-C. Lin, G.-W. Lee, J.-D. Huang, and J.-Y. Jou, "A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses," in Asia and South Pacific Design Automation Conference, 2007, pp. 165-170.

[25] "SoC Designer Developer Guide," www.arm.com.

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