Experimental Result

The output stage is described in Chapter Two. Note that there is only one pad used to read out the state voltage of all 81 pixels. Therefore, a column decoder and a row decoder are employed here to read out all 81 pixels one by one in series.

The summary comparison of this work - ARMCNN w/o EO and the previous work – RMCNN w/o EO is shown in Table 4.2. Note that both of them do not have elapsed operation.

Previous Work This Work

Technology 0.35um 2P4M

Mixed-Signal Process

Single pixel area 400um x 250um 205um x 185um

RMCNN 9x9 array (include pad) 4560 um x 3900um 2240 x 2240

Number of Pins 81 pins 51 pins

Power supply 3V 3V

Learning power dissipation N/A (large) 102mW

Recognition power dissipation 87mW 72mW

Quiescent power dissipation N/A (large) 39mW

Readout time 100ns 100ns

Power Lines N/A Analog: 2 pairs

Digital: 2 pairs Ext. I/O: 1 pairs Table 4.2 the summary comparison of this work and the previous work

The output voltage levels of black and white are defined in section 3.2, where black pixel is 0.97V – 0.05V = 0.92V and white pixel is 0.43V + 0.05V = 0.48V.

The output of each pixel is read out column by column sequentially. The first column is read from top to bottom and then the second column and so on. Fig 4.6 shows the noisy input pattern “四” that is feed in for recognition and recovery and its presim and measurement result. Fig 4.7 and Fig 4.8 are the input patterns, the pre-simulation results, and the measurement results of the case “二” and “一”, respectively.

Fig 4.6 (a) noisy pattern “四” is inputted for recovery (b) (c) experimental result of recognition and recovery

Fig 4.7 (a) noisy pattern “二” is inputted for recovery (b) (c) experimental result of recognition and recovery

(a) (b)

(c)

Fig 4.8 (a) noisy pattern “一” is inputted for recovery (b) (c) experimental result of recognition and recovery

4.4 Cause of the Imperfect Experiment Result

Fig 4.9 The diagram of the top left 3 x 3 cell arrays

The measurement results of all three characters show imperfection on the first row and the second row first column, which also appears in the post-simulation. Further investigation found that because in this work, a pixel consists of one cell and two RM blocks (UP and LEFT). Therefore, after 9 x 9 cell arrays are put together, there will have redundant RM blocks on the leftmost and the topmost cells, which might generated the undesired weights.

Fig 4.9 shows the top left 3 x 3 cell arrays, where the number inside the circle means the cell output’s contribution factor to its neighbors and the lines between cells means two cells are having relation. If the leftmost and the topmost cells’ color never change, then unwanted weights will be generated on the redundant RM blocks. Fig 4.10 (a) is the desired ratio weights of 3 x 3 cell arrays in Fig 4.9. Fig 4.10 (b) shows how the redundant RM blocks contributes the undesired weights and lead to wrong ratio weights.

To solve this problem, redundant RM blocks must be removed to avoid undesired weights contributed from redundant RM blocks.

Fig 4.10 (a) desired ratio weights of Fig 4.9 (b) actual ratio weights due to redundant RM blocks

Fig 4.11 is the presim recognition result of pattern ‘四’ for both the original design and the modified design. It is clear that in the modified version of design, the imperfection on every column’s first element is fixed. Fig 4.12 and Fig 4.13 are the presim recognition result of pattern ‘二’ and ‘一’.

Fig 4.11 Presim results of pattern ‘四’ for the original design and the modified design.

Fig 4.12 Presim results of pattern ‘二’ for the original design and the modified design.

Fig 4.13 Presim results of pattern ‘一’ for the original design and the modified design.

CHAPTER 5

CONCLUSION AND FUTURE WORK

5.1 Conclusion

A novel Autonomous RMCNN without elapsed operation is implemented. The modified Hebbian learning rule with strongest weight comparison is proposed. The new design not only inherits the advantage of the RMCNN, such as longer memory time, and image feature enhancement, but also the die area shrinks to only 0.28 times of the original design, which makes it feasible to be implemented on chip. Furthermore, all three patterns “一、二、四” can be successfully recognized and recovery.

During recognition phase, the noisy input now precharges into state capacitor rather than constantly injects to cells, which is proven to improve the recognition rate as the environmental noise raises. In addition, the proposed Hebbian learning rule ensures only the strongest weights remains instead of comparing with a mean value of abs weight in a local matrix.

The ARMCNN does not require additional elapsed phase to achieve the feature enhancement of the ratio weight. The ARMCNN uses logic operation to generate the feature enhance ratio weights directly after patterns are learned, which simplifies the complexity of the design and reduce the operation time. More importantly, it yields the same recognition rate comparing with the design with elapsed operation.

The total number of the learning patterns of ARMCNN is three. They are Chinese characters one, two and three （一、二、四）. According to the simulation results by C language,

ARMCNN yields a better recognition rate when the environmental noise increases and when the total number of the learning patterns increases to four.

In addition, the design has fixed the problem that a small current charges / discharges the stored weights during pattern transferring. The dynamic flip-flop (DFF) in the previous work, RMCNN w/o EO has caused dc power consumption problem. Thus, in this work, the DFF has been replaced by the static flip-flop. Besides, the detector circuit is also modified to cutoff a huge amount of quiescent power (from 32mW to 4mW).

5.2 Future Work

The ARMCNN w/o EO in this thesis can recognize all of the three patterns. However, the redundant RM blocks cause some imperfection on the boundary cells. The modified circuit should be taped out again. Moreover, there are six switches used in the local counters and they are controlled by the combination logic from the global counter. However, the total number of switches used in the local counters can reduce to four. By doing so, we can make the layout routing easier. The controlling signals and total number of pins used are still too many (51 pins in this work), which makes the measurement and design more complicate. It is possible to reduce 9 input pins to 1 input pins and on-chip generated 3 reference voltage of (1/2 VDD). Some controlling signals can be combined together to reduce the control signals used. It can reduce 13 pins. The idea of replacing circuits for learning behavior and ratio weights generation with digital circuits might greatly reduce the die area. Because now we use many capacitors to store the weights and many analog circuits to perform learning behavior, it not only takes space, but also increase the possibility of getting errors. The total elements saved are: 144 capacitors (>1pF), 144 T3 and 144 COMP circuits, 81 T1 and T2D circuits.

Accordingly, it can reduce about a half of the chip area.

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簡歷

姓 名：周 維 德 學 歷：

Burnaby Central Secondary School (85年 9 月 ~ 89 年 6 月) University of British Columbia (89年 9 月 ~ 93 年 6 月) 國立交通大學電子研究所碩士班 (94年 9 月 ~ 96 年 12 月)

研究所修習課程：

類比積體電路 I、II 吳介琮教授

數位積體電路 周世傑教授

積體電路之靜電放電防護設計特論 柯明道教授

矽智產設計 黃俊達教授

計算機輔助設計特論 周景陽教授

功率積體電路設計 陳科宏教授

混合訊號式積體電路設計與實驗 I 吳介琮教授

穩健設計之品質工程 黎正中教授

永久地址： 台北市光復南路568-1號12F Email： [email protected]

[email protected]