Conclusion

A novel Autonomous RMCNN without elapsed operation is implemented. The modified Hebbian learning rule with strongest weight comparison is proposed. The new design not only inherits the advantage of the RMCNN, such as longer memory time, and image feature enhancement, but also the die area shrinks to only 0.28 times of the original design, which makes it feasible to be implemented on chip. Furthermore, all three patterns “一、二、四” can be successfully recognized and recovery.

During recognition phase, the noisy input now precharges into state capacitor rather than constantly injects to cells, which is proven to improve the recognition rate as the environmental noise raises. In addition, the proposed Hebbian learning rule ensures only the strongest weights remains instead of comparing with a mean value of abs weight in a local matrix.

The ARMCNN does not require additional elapsed phase to achieve the feature enhancement of the ratio weight. The ARMCNN uses logic operation to generate the feature enhance ratio weights directly after patterns are learned, which simplifies the complexity of the design and reduce the operation time. More importantly, it yields the same recognition rate comparing with the design with elapsed operation.

The total number of the learning patterns of ARMCNN is three. They are Chinese characters one, two and three （一、二、四）. According to the simulation results by C language,

ARMCNN yields a better recognition rate when the environmental noise increases and when the total number of the learning patterns increases to four.

In addition, the design has fixed the problem that a small current charges / discharges the stored weights during pattern transferring. The dynamic flip-flop (DFF) in the previous work, RMCNN w/o EO has caused dc power consumption problem. Thus, in this work, the DFF has been replaced by the static flip-flop. Besides, the detector circuit is also modified to cutoff a huge amount of quiescent power (from 32mW to 4mW).

5.2 Future Work

The ARMCNN w/o EO in this thesis can recognize all of the three patterns. However, the redundant RM blocks cause some imperfection on the boundary cells. The modified circuit should be taped out again. Moreover, there are six switches used in the local counters and they are controlled by the combination logic from the global counter. However, the total number of switches used in the local counters can reduce to four. By doing so, we can make the layout routing easier. The controlling signals and total number of pins used are still too many (51 pins in this work), which makes the measurement and design more complicate. It is possible to reduce 9 input pins to 1 input pins and on-chip generated 3 reference voltage of (1/2 VDD). Some controlling signals can be combined together to reduce the control signals used. It can reduce 13 pins. The idea of replacing circuits for learning behavior and ratio weights generation with digital circuits might greatly reduce the die area. Because now we use many capacitors to store the weights and many analog circuits to perform learning behavior, it not only takes space, but also increase the possibility of getting errors. The total elements saved are: 144 capacitors (>1pF), 144 T3 and 144 COMP circuits, 81 T1 and T2D circuits.

Accordingly, it can reduce about a half of the chip area.

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簡歷

姓 名：周 維 德 學 歷：

Burnaby Central Secondary School (85年 9 月 ~ 89 年 6 月) University of British Columbia (89年 9 月 ~ 93 年 6 月) 國立交通大學電子研究所碩士班 (94年 9 月 ~ 96 年 12 月)

研究所修習課程：

類比積體電路 I、II 吳介琮教授

數位積體電路 周世傑教授

積體電路之靜電放電防護設計特論 柯明道教授

矽智產設計 黃俊達教授

計算機輔助設計特論 周景陽教授

功率積體電路設計 陳科宏教授

混合訊號式積體電路設計與實驗 I 吳介琮教授

穩健設計之品質工程 黎正中教授

永久地址： 台北市光復南路568-1號12F Email： [email protected]

[email protected]