The GA-based algorithm is implemented in Programming Language Interface (PLI) environment. Experiments are conducted over a set of ISCAS-85 and some MCNC benchmarks. Table 5.1 summarizes the experimental results of the previous approach in [38] and our GA-based algorithm. The first four columns show the parameters of each benchmark, including name, |PI|, |PO| and the number of literals (lits.). The |PI|
represents the number of inputs. The |PO| represents the number of outputs. The number of literals indicates the complexity of a benchmark. This number is derived from its gate level description. The remaining columns show the sets of inputs that cannot be distinguished. In fact, these input sets are possibly symmetric inputs sets. They are expressed by pairs (size, number of sets), where size is the size of an input set and the following is the number of sets of that size. For example, for c880, three sets of size two means that they are possible symmetric inputs and the other sets of size one means that the 54 inputs are asymmetric to other inputs. The iteration bound is set to 100. The CPU time is measured in second on a SUN Sparc II workstation. The algorithm will be terminated automatically if iterations are over the bound or all inputs are nonsymmetric, and SASIs are returned. According to Table 5.1, we can find that in previous approach, c499, c1355, and c1908 still have potentially symmetric input sets, but our approach can distinguish each input as a nonsymmetric input. Also for c2670 and c6288, our approach distinguishes more nonsymmetric inputs than that of [38]. Please note for c6288, our approach does not distinguish each input as a nonsymmetric input while [38] does. This is because our heuristic patterns inherently cannot distinguish each input of a multiplier such as c6288. [38] uses test generation technique to conquer it instead. Table 5.2 also shows the results on some MCNC benchmarks. Most nonsymmetric inputs are distinguished efficiently as usual for most benchmarks. These results demonstrate that our approach acts as a good filter to identify nonsymmetric inputs as many as possible in a circuit such that significant efforts can be saved for other succeeding applications.
Our approach is applicable to sequential circuits if circuit states can be fully specified.
The experiments on sequential circuits are progressing.
Table 5.1. Comparisons on experimental results of previous approach in [38] and GA approach.
Parameters Previous approach in
[38] GA approach
Table 5.2. Results of some MCNC benchmarks.
Chapter 6
Conclusions
In the SoC era, the embedded cores are mixed and integrated to create a system chip. The verification of the core-based system design should be focused on how the cores communicate with each other. However, before the interface verification, the interconnections between the cores in an SoC have to be verified first. System integrators integrate those cores manually and have the possibility of incorrect integration due to the misplaced I/O ports. Therefore, we adopt the connectivity-based POE model to raise the abstraction level of the design verification and to reduce the time on functional verification in core-based design methodology.
In this thesis, we present a new pattern generation algorithm to activate all
remaining POEs and the GA technique to improve the UPSs_Calculation procedure.
These two approaches get more precise remaining UPSs and therefore accelerate the AVPG and generates a more efficient verification pattern set for verifying core-based designs.
Besides, we use this GA technique for computing maximal sets of symmetric inputs of circuits. It can be used to identify nonsymmetric inputs in a circuit and enhance the efficiency of input matching, library binding (technology mapping), as well as logic verification problems. The experimental results demonstrate that our approach distinguishes more nonsymmetric inputs than that of previous work.
References
[1] M. Abramovici, M. A. Breuer, and A. D. Friedman, “Digital Systems Testing and Testable Design,” Computer Science Press, 1990, pp. 95.
[2] M. Agrawal and V. Arvind, “A Note on Decision Versus Search for Graph Automorphism,” in Eleventh Annual IEEE Conference Computational Complexity, 1996, pp. 272–277.
[3] H. Chang, L. Cooke, M. Hunt, G. Martin, A. McNelly, and L.Todd, Surviving the SOC Revolution—A Guide to Platform-Based Design. Norwell, MA: Kluwer, 1999.
[4] R. Chang, W. Gasarch, and J. Toran, “On Finding the Number of Graph Automorphism,”
in IEEE Structure in Complexity Theory Conference, 1995, pp. 288–298.
[5] D. I. Cheng and M. Marek-Sadowska, “Verifying Equivalence of Functions with Unknown Input Correspondence,” in Proceedings European Design Automation Conference (EDAC), 1993, pp. 81-85.
[6] K.-T. Cheng, and J.-Y. Jou, ”A Functional Fault Model for Sequential Machines,” IEEE Transactions on Computer-Aided Design, Sep. 1992, pp.1065-1073.
[7] P. Goel and M. T. McMahon, “Electronic Chip-in-place Test,” in Proceedings IEEE International Test Conference, Oct. 1982, pp. 83–90.
[8] A. Hassan, V. K. Agarwal, B. Nadeau-Dostie, and J. Rajski, “BIST of PCB Interconnects Using Boundary-scan Architecture,” IEEE Transactions Computer-Aided Design, Oct.
1992, pp. 1278–1288.
[9] H.-T. Liaw, J.-H. Tsaib and C.-S. Lin, “Efficient Automatic Diagnosis of Digital Circuits,” International Conference On Computer-Aided Design, Nov. 1990, pp.464-467.
[10] J. C. Madre, O. Coudert and J. P. Billon, “Automating the Diagnosis and the Rectification of Design Errors with PRIAM,” in Proceedings International Conference on Computer-Aided Design, Nov. 1989, pp. 30-33.
[11] J. Mohnke and S. Malik, “Permutation and Phase Independent Boolean Comparison,” in Proceedings European Design Automation Conference (EDAC), 1993, pp. 86-92.
[12] I. Pomeranz and S. M. Reddy, “On Diagnosis and Correction of Design Errors,” in Proceedings International Conference On Computer-Aided Design, Nov 1993.
[13] J. A. Rowson and A. Sangiovanni-Vincentelli, “Interface-Based Design,” in Proceedings Design Automation Conference, June 1997, pp. 178–183.
[14] U. Schlichtmann, F. Brglez and M. Hermann, “Characterization of Boolean Functions for Rapid Matching in EPGA Technology Mapping,” in Proceedings Design Automation Conference, June 1992, pp. 374-379.
[15] M. H. Schulz, E. Trischler, and T. M. Sarfert, ”SOCRATES: a Highly Efficient Automatic Test Pattern Generation System,” IEEE Transactions on Computer-Aided Design, Jan. 1988, pp.126-137.
[16] K.A. Tamura, “Locating Functional Errors in Logic Circuits,” in Proceedings Design Automation Conference, 1989, pp. 185-191.
[17] S.-W. Tung and J.-Y. Jou, “A Logic Fault Model for Library Coherence Checking,”
Journal of Information Science and Engineering, Sept. 1998, pp. 567–586.
[18] C.-Y. Wang, S.-W. Tung, and J.-Y. Jou, “On Automatic-verification Pattern Generation for SoC with Port-order Fault Model,” IEEE Transactions on Computer-Aided Design, vol. 21, Apr. 2002, pp. 466–479.
[19] C.-Y. Wang, S.-W. Tung, and J.-Y. Jou, “An Automorphic Approach to Verification Pattern Generation for SoC Design Verification Using Port-Order Fault Model,” IEEE Transactions on Computer-Aided Design, vol. 21, Oct. 2002, pp. 1225–1232.
[20] D. B. West, ”Introduction to Graph Theory,” Upper Saddle River, New Jersey, Prentice-Hall, Incorporation, 1996.
[21] M. S. Abadir, J. Ferguson, and T. E. Kirkland, “Logic Design Verification via Test Generation,” IEEE Transactions on Computer, Jan. 1988, pp. 138-148.
[22] R. E. Bryant, “Graph-based Algorithms for Boolean Function Manipulation,” IEEE Transactions on Computer, Aug. 1986, pp. 677-691.
[23] P. Camurati and P. Prinetto, “Formal Verification of Hardware Correctness: Introduction and Survey of Current Research,” IEEE Computer, July 1988, pp. 8-19.
[24] D. I. Cheng and M. Marek-Sadowska, “Verifying Equivalence of Functions with Unknown Input Correspondence,” in Proceedings of European Design Automation Conference (EDAC), 1993, pp.81-85.
[25] P. Y. Chung and I. N. Hajj, “ACCORD: Automatic Catching and Correction of Logic Design Errors in Combinational Circuits,” in Proceedings of International Test Conference, 1992, pp. 742-751.
[26] S. Devadas, H. K. T. Ma, and A. R. Newton, “On the Verification of Sequential Machinesat Differing Levels of Abstraction,” IEEE Transactions on Computer-Aided Design, June 1988, pp. 713-722.
[27] J. Jain, J. Bitner, D. S. Fussell, and J. A. Abraham, “Probabilistic Design Verification,” in Proceedings of International Conference Computer-Aided Design, Nov. 1991, pp.
468-471.
[28] K. Keutzer, “DAGON: Technology Binding and Local Optimization by DAG Matching,”
in Proceedings of Design Automation Conference, 1987, pp. 341-347.
[29] S. Y. Kuo, “Locating Logic Design Errors via Test Generation and Don’t-care Propagation,” in Proceedings of European Design Automation Conference (EDAC), Sep.
1992, pp. 466-471.
[30] H. T. Liaw, J. H. Tsaih, and C. S. Line, “Efficient Automatic Diagnosis of Digital Circuits,” in Proceedings of International Conference Computer-Aided Design, Nov.
1990, pp. 464-467.
[31] J. C. Madre, O. Coudert, and J. P. Billon, “Automating the Diagnosis and the Rectification of Design Errors with PRIAM,” in Proceedings of International Conference Computer-Aided Design, Nov. 1989, pp. 30-33.
[32] F. Maruyama and M. Fujita, “Hardware Verification,” IEEE Computer, Feb. 1985, pp.
22-32.
[33] E. J. McCluskey, “Detection of Group Invariance or Total Symmetry of a Boolean Function,” Bell System Tech, J., Nov. 1956, pp. 1445-1453.
[34] E. J. McCluskey, Logic Design Principles with Emphasis on Testable Semicustom Circuits, Prentice-Hall, 1986.
[35] Alan Mishchenko, “Fast Computation of Symmetries in Boolean Functions” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No.
11, Nov. 2003, pp. 1588-1593.
[36] J. Mohnke and S. Malik, “Permutation and Phase Independent Boolean Comparison,” in Proceedings of European Design Automation Conference (EDAC), 1993, pp. 86-92.
[37] D. Moller, J. Mohnke, and M. Weber, “Detection of Symmetry of Boolean Functions Represented by ROBDDs,” in Proceedings of International Conference Computer-Aided Design, Nov. 1993, pp. 608-684.
[38] I. Pomeranz and S.M. Reddy, “On Determining Symmetries in Inputs of Logic Circuits,”
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.
13, No. 11, Nov. 1994, pp. 1428-1434.
[39] U. Schlichtmann, F. Brglez., and M. Hermann, “Characterization of Boolean Functions for Rapid Matching in EPGA Technology Mapping,” in Proceedings of Design Automation Conference, June 1992, pp. 347-379.
[40] K. A. Tamura, “Locating Functional Errors in Logic Circuit,” in Proceedings of Design Automation Conference, 1989, pp. 185-191.
[41] M. Tomita, H. H. Jiang, T. Yamamoto, and Y. Hayashi, “An Algorithm for Locating Logic Design Errors,” in Proceedings of International Conference Computer-Aided Design, Nov. 1990, pp. 468-471.
[42] R. L. Wadsack, “Design Verification and Testing of the WE 32100 CPUs,” IEEE Design and Test, Aug. 1984, pp. 66-75.
[43] R, S. Wei and A. L. Sangiovanni-Vincentelli, “PROTEUS: A Logic Verification System for Combinational Circuits,” in Proceedings of International Test Conference, Sep. 1986, pp. 350-359.
[44] A. S. Wojcik, “Formal Design Verification of Digital Systems,” in Proceedings of Design Automation Conference, June 1983, pp. 228-234
Vita
Chen-Ling Chou was born in Taipei, Taiwan on August 2, 1980. She received the M.S. degree in Electrical and Control Engineering from National Chiao Tung University in June 2002 and entered the Institute of Electronics, National Chiao Tung University in September 2002. Her major studies were Electronics Design Automation (EDA) and VLSI design. She received the M.S. degree from NCTU in June 2004.