There are two platforms for us to download our baseband codes and perform the advanced verification. In order to take account of interaction between other modules such as DSP, USB, and AD/DA on these two platforms, modification needs to be executed frequently. Therefore to synthesis, map, and place and route iteratively seems to be unavoidable and always waste a lot of time. Besides time consuming, the insufficiency of FPGA gate count becomes another problem, especially on the VBLAST receiver side. Therefore we must try our best to save gate count, and that is an important reason why we try to find out a quantization algorithm that can minimize the hardware resource requirement. Table 4.3 shows time and area consumption in our developing flow, where whole design flow including developing transmitter and receiver takes 2 to 4 hours. Therefore to test a system is quite time consuming.
Table 4.2: Synthesis and P&R information
59717 (88%) Rx (Virtex2 6000)
NA 40mins 42mins Tx (VirtexE 2000)
1hr 30mins
Place and Route Time
Rx (Virtex2 6000) Tx (VirtexE 2000)
59717 (88%) Rx (Virtex2 6000)
NA 40mins 42mins Tx (VirtexE 2000)
1hr 30mins
Place and Route Time
Rx (Virtex2 6000) Tx (VirtexE 2000)
4.5.1 Fast Prototyping Platform
In the fast prototyping platform, we successfully integrate FPGA, DSP, USB, and AD/DA modules. First the web camera catches the real time images continuously as the data source, and then passes it to DSP module. DSP, without any processing, directly pass the data to FPGA, and FPGA performs MIMO-OFDM transmitter algorithm. After the processing of transmitter, data are passed through DA and received by AD. Subsequently AD passes data to receiver FPGA, and start to decode the received data. Finally, the decoded data are sent back to PC through DSP and USB module, and shows through the self-developed application software in PC. We can provide an user interface to demonstrate the real time transmitted and received images, as shown in Figure 4.35. In this figure, a 3×3 images set is located. The three columns represent transmit images, receive images, and error images respectively, whereas the three rows represent the synthesized images of all antennas, first antenna, and second antennas respectively. The real time bit error rate is also calculated and shown in the right hand side.
Figure 4.35: Prototyping platform experimental result
4.5.2 Self-designed Platform
In the self-designed platform, we attempt to establish a real wireless environment, under which the adopted algorithm can be tested. Figure 4.36 shows the experimental environment which has been shown in Chapter 3. First, source data are stored in a ROM in FPGA, and passed to DA after processing by transmitter algorithm on FPGA.
Next, data are transmitted on the 5.2 GHz frequency band by the RF module, and a receive antenna is allocated near the RF module. Subsequently data are received by the receive antenna and passed to spectrum analyzer E4443A and vector signal analyzer 89600S. Finally, received data are analyzed and shown on PC. Figure 4.37 shows the analyzed result, which can represent the effects of a real wireless channel. We can see that in frequency domain, the measured center frequency is 5.200152 GHz, and the occupied bandwidth (OBW) is approximately 20 MHz. In time domain, due to the mismatch between mixers in transmitter and receiver, preamble data (only transmitted in real part) is distributed into real and image parts in the receiver. Otherwise, owing to the effect of frequency offset, the slight swing in envelop of received data also can be observed.
Figure 4.36: Self-designed platform development environment
Figure 4.37: Self-designed platform experimental result: received spectrum and waveforms on PSA and VSA
After the received data pass through AD converter, all signals are digitalized and therefore can be measured by the logic analyzer easily. Figure 4.38 shows the waveform of timing synchronizer measured by the logic analyzer. As simulated in MATLAB and ModelSim, timing synchronization output forms a hill and the peak time index is regarded as the packet start time.
Frame start
offset frame time - offset
Frame start Peak
offset frame time - offset
Peak
Figure 4.38: Self-designed platform experimental result: timing synchronization waveform on LA
Figure 4.39 shows the source data stream in transmitter, transmitted data stream, and detected data stream in the receiver, where the source data stream and the detected data stream are specially expanded below. By comparing the source data stream with detected data stream we can find out that they are exactly the same, which confirms that our algorithm does work successfully.
Figure 4.39: Self-designed platform experimental result: source data and detected data waveform on LA
4.6 Summary
In this chapter, a complete communication system design flow is proposed, including MATLAB verification, FPGA realization, ModelSim simulation, and experimental results. Through this design flow, we finish developing a 2 × 2 MIMO-OFDM system on two FPGA-based platforms, e.g., fast prototyping platform and self-designed platform. On the fast prototyping platform, we integrate our communication algorithm with web camera, and demonstrate real time video on the self-developed software interface. On the self-designed platform, real wireless channel effects can be generated by means of RF module, and some RF debugging instruments, which makes our system become much closer to real communication system.
Chapter 5
Proposed Quantization Algorithm with Minimum Hardware
Requirement
The algorithms used by DSP systems are typically specified as floating-point DSP operations. On the other hand, most digital FPGA implementations of these algorithms rely solely on fixed-point approximations to reduce the cost of hardware while increasing throughput rates. The essential design step of floating-point to fixed-point conversion is not only time consuming, but also complicated due to the nonlinear characteristics and the massive design optimization space. In a bid to achieve short product cycles, the execution of floating to fixed-point conversion is often left to hardware designers, who are familiar with VLSI constraints. Comparing with the algorithm designers, this group often has less insight into the algorithm and depends on ad hoc approaches to evaluate the implications of fixed-point representations. The gap between algorithm and hardware design is even aggravated as algorithms continue to become more complex. Thus, a systematical method for floating to fixed-point conversion is urgently called for.
In this chapter, a quantization algorithm which is especially suitable for communication systems is proposed, where hardware resources are minimized, and the equivalent quantization error is constrained within a specified limit.