In this chapter, a surface micromachining-like fabrication process is described.
The SU-8 photoresist is used with silicon-on-insulator (SOI) wafers to simplify the process flow. The SOI wafer is chosen with its flat surface characteristic of single crystal silicon. Using SOI wafers can also reduce the complexity of the process. SU-8 photoresist is used as a structure layer. Compared to the use of polysilicon as the structure layer, SU-8 photoresist can reduce the process complexity. Another advantage of using SU-8 is that the process temperature is low, which is more compatible with IC processes. However, the Young’s modulus of SU-8 is about 4 GPa, while that of polysilicon is about 160 GPa. Therefore the deformation of SU-8 is larger than polysilicon under the same stress. Therefore, SU-8 structures should be well designed for angular positioning, as discussed in Chapter 2. The process of integration of SOI wafer with SU-8 photoresist is described in the following. The fabrication parameters are listed and some issues are discussed.
3-1 Process flow
As described in Chapter 2, SU-8 photoresist is used as a structure layer for angular positioning in Device 1. Therefore, the fabrication process includes both SOI wafers and SU-8 photoresist. In contract to Device 1, the device layer of the SOI wafer is used for angular positioning in Device 2. Consequently, the fabrication process is simpler in Device 2 without using SU-8 photoresist.
SOI Substrate
Single crystal silicon layer
Buried oxide
SOI Substrate SOI Substrate
Buried oxide 3-1-1 Device 1
The fabrication process of Device 1 is shown in Figure 3-1. The device was fabricated in the Nano Facility Center at National Chiao Tung University. The SOI wafers have a device layer of 5 µm, buried oxide layer of 2 µm, and handle layer of 400 µm.
(a) RCA cleaning (Step A)
(b) Front side patterning (Step B, Step C)
(c) Backside oxide deposition (Step D)
Figure 3-1 Fabrication process (Device 1).
Buried oxide PECVD Oxide
SOI Substrate
Buried oxide
SOI Substrate
SOI Substrate
SOI Substrate
Buried oxide
(d) Anchor definition (Step E, Step F)
(e) Oxide deposition, anchor patterning (Step G, Step H, Step I)
(f) Backside oxide definition (Step J, Step K)
(g) SU-8 coating (Step L)
Figure 3-1 Fabrication process (Device 1) (continued).
PECVD Oxide
Buried oxide PECVD Oxide
Buried oxide PECVD Oxide AZ4620 photoresist
PECVD Oxide SU-8 photoresist No over etching
Buried oxide
(h) Backside ICP etching (Step N)
(i) Oxide release (Step O)
(j) Push (Step P)
Figure 3-1 Fabrication process (Device 1) (continued).
Step A: RCA cleaning
A standard RCA clean process was first performed on the bare SOI wafer. The process will remove the organic contaminants, the native oxide layer, and the ionic
PECVD Oxide SU-8 photoresist
SOI Substrate
SU-8 photoresist
contaminants. Detailed parameters are shown below. In consideration of the buried oxide in the SOI wafer, the chemical oxide removal process is reduced to 30 seconds.
Between each step is de-ionized water rinse.
Step B: Photolithography – Device layer definition (Mask1)
The FH6400 positive photoreisit is coated on the SOI wafer as the etching mask for defining the device layer by inductively coupled plasma (ICP). Mask 1 defines the main structure on the 5-µm-thick device layer. Detailed parameters are listed as below
Step Description Parameters
0 Photoresist FH6400
1 HMDS coating Vapor prime oven
Coating (spread cycle) 1000 rpm 10 sec
2 Coating (spin cycle) 2000 rpm 35 sec
3 Soft bake 90° C hotplate 150 sec
4 Exposure Karl Suss MJB-3 mask aligner (3.2 mW/cm2) for 90 sec
5 Development Developer FHD-5 for 55 sec
6 Rinse D.I. water 1 min
7 Hard bake 120° C hotplate 30 min
Step C: Inductively coupled plasma silicon etching
Inductively coupled plasma (ICP) is used to etch the 5-µm-thick silicon device
layer with the mask defined in Step B. This process is performed by the ICP etching service of ITRC (Instrument Technology Research Center) and NTU (National Taiwan University). The parameters of the ICP etching at NTU (STS MESC multiplex ICP) are listed below.
Description Etch phase parameters Passivation phase parameters
Time per cycle 11.5 seconds 7.0 seconds
SF6 flow rate 130 sccm 0 sccm
Helium backside pressure = 10 torr Maximum helium leak up rate = 20 mtorr/min Etch rate 0.6-0.7 µm per cycle depending on pattern
Step D: Backside silicon oxide deposition
Silicon oxide is deposited by a BR-2000LL plasma enhanced chemical vapor deposition (PECVD) system on the backside of the handle layer. The deposited oxide layer with a thickness of 4.5 µm will be used as a hard mask for 400 µm ICP etching process. The thickness of the oxide layer is determined according to the 1:100 selectivity between the oxide and the silicon in the ICP process.
Description Parameters
Deposition time Two 35-minute deposition for 2.25 µm each
Step E: Photolithography – Anchor definition (Mask 2)
The anchor pattern is defined with Mask 2 in AZ4620 positive photoresist. The 2- µm-thick buried oxide layer of the SOI wafer is then etched by RIE. The selectivity between buried oxide and the AZ4620 photoresist is about 1:2 in the RIE process.
Therefore, 5-µm-thick photoresist is coated in this step.
Step Description Parameters
0 Photoresist AZ4620
1 HMDS coating Vapor prime oven
Coating (spread cycle) 1000 rpm 10 sec
2 Coating (spin cycle) 2500 rpm 30 sec
3 Soft bake 90° C hotplate 25 min
4 Exposure Karl Suss MJB-3 mask aligner (3.2 mW/cm2) for 350 sec
5 Development Developer AZ-300 for 4 min 35 sec
6 Rinse D.I. water 1 min
7 Hard bake 120° C hotplate 60 min
Step F: Polysilicon reactive ion etching (Poly-Si RIE) – Buried oxide etching
The buried oxide layer exposed in Step E is etched by RIE (SAMCO RIE-10N).
The 2-µm-thick oxide in the anchor areas is removed in this step to ensure the contact and adhesion between the SU-8 and the silicon.
Description Parameters
SF6 flow rate 30 sccm
CHF3 flow rate 10 sccm
Helium backside cooling about 15 sccm
Process pressure 50 mtorr
RF power 100 W
Etch rate 20 min for 2 µm buried oxide
Step G: Front side silicon oxide deposition
The sacrificial oxide layer between the SU-8 and the silicon device layer of the SOI wafer is deposited on the front side in this step by PECVD. The buried oxide and the silicon oxide deposited in this step provide the hinge pin rotation space after releasing. The deposition thickness is 3 µm.
Description Parameters
Deposition time Two 23-minuate deposition for 1.5 µm each
Step H: Photolithography – Anchor definition (Mask 3)
Similar to Step E, anchor is defined again in this step. The oxide deposited in the previous step will be etched in the next step with the pattern defined in this step. Since the selectivity between PECVD oxide and AZ4620 photoresist is about 1:1.7 in the RIE process, a 7-µm-thick photoresist of AZ4620 is coated on the wafer.
Step Description Parameters
0 Photoresist AZ4620
1 HMDS coating Vapor prime oven
Coating (spread cycle) 1000 rpm 10 sec
2 Coating (spin cycle) 2000 rpm 30 sec
3 Soft bake 90° C hotplate 28 min
4 Exposure Karl Suss MJB-3 mask aligner (3.2 mW/cm2) for 350 sec
5 Development Developer AZ-300 for 4 min 35 sec
6 Rinse D.I. water 1 min
7 Hard bake 120° C hotplate 60 min
Step I: High density plasma reactive ion etching (HDP-RIE) – PECVD oxide etching This step defines the contact between the silicon device layer and the SU-8 layer.
About 3-µm-thick oxide deposited by PECVD is etched. To prevent etching of the silicon device layer, HDP-RIE is used for its good selectivity between the silicon and oxide in this step. Thus the 5-µm-thick silicon will not be etched, as marked in Figure 3-1 (e). The prolonged etching time can ensure the complete removal of the oxide on the silicon device layer and silicon substrate.
Description Parameters
Step J: Photolithography on backside silicon oxide (Mask 4)
The wafer through hole is defined in this step as the space for pushing. The oxide layer is deposited in Step D. This step patterns the oxide by AZ4620 photoresist. The patterned oxide will be used as the hard mask for etching the 400 µm silicon on the backside of the SOI wafer. An EV620 double side aligner at National Tsing Hua University (NCTU) is used for the photolithography process. About 8 µm photoresist is coated in this step.
Step Description Parameters
0 Photoresist AZ4620
1 HMDS coating Vapor prime oven
2 Coating (spread cycle) 1000 rpm 10 sec
Coating (spin cycle) 2000 rpm 40 sec
3 Soft bake 90° C hotplate 27 min
4 Exposure EV620 mask aligner (10 mW/cm2) for 12 sec
5 Development Developer for 1 min 15 sec
6 Rinse D.I. water 1 min
7 Hard bake 120° C hotplate 60 min
Step K: Polysilicon reactive ion etching (Poly-Si RIE) – Backside oxide etching The patterned 4.5 µm oxide is etched in this step. Over etching is also needed to ensure complete removal of the oxide on the silicon. The selectivity between the PECVD oxide and the AZ4620 photoresist is 1:1.8.
Description Parameters
SF6 flow rate 30 sccm
CHF3 flow rate 10 sccm
Helium backside cooling about 15 sccm
Process pressure 50 mtorr
RF power 100 W
Etch rate 18 min for 2 µm PECVD oxide
Step L: SU-8 photolithography (Mask 5) – SU-8 structure layer definition
The 13-µm-thick SU-8 negative photoresist is deposited as a structure layer by Mask 5 in this step. This step is important for angular accuracy of the device.
However the aligner used to fabricate the devices has a alignment accuracy of 2 µm, so the accuracy for the final device may be limited.
Step Description Parameters
0 Photoresist SU-8 2010
1 Native oxide remove BOE 10 sec (etching rate: 1000 Å/min)
2 Pre-bake 150° C hotplate 20min
3 Coating (spread cycle) 500 rpm 10 sec
Coating (spin cycle) 3000 rpm 30 sec
7 Development SU-8 Developer for 3 min
8 Rinse IPA 1 min
9 Hard bake 200° C hotplate for 30 min
Step M: Wafer dicing
The wafer is then diced into individual device chips. Since the subsequent ICP etching depth is nearly the depth of the whole wafer, only chips are used to reduce the risk of breaking the whole wafer in the ICP chamber.
Step N: Backside inductively coupled plasma deep silicon etching
The diced chips are bonded to a carrier wafer with thermal grease before the ICP etching. Thermal grease was used to cover all sides of the chip to prevent the front side of the chip from being etched by the plasma leaking through the uncovered gap between the chip and the carrier wafer. Oxide is deposited on the carrier wafer as the shield during ICP process. The 400-µm-thick silicon substrate is then etched. The diced device bonded to the carrier wafer will change the helium cooling conditions and affect the vertical profile of the etched side wall. However, the etched through hole is only used for the next assembly process, so its vertical profile is not critical.
Hence identical etching parameters as in Step C are used in this step. The process is done by the ICP etching service of ITRI and NTU.
Step O: Device release
The final step of the fabrication process is to etch the oxide layer to suspend the structure. This step is very important since the large mirror plate can easily stick to the substrate in conventional releasing process with HF solution. Vapor HF releasing is generally acknowledged as the method to solve the problem of stiction without using aqueous HF etching and DI water rinsing [29].
The parameters of the vapor HF releasing are shown in Table 3-1, and the schematic of the apparatus is shown in Figure 3-2. The apparatus consists of a light bulb, two polymer (such as polypropylene) cups, of which the inside one is hollow in the bottom, one polymer net, and one polymer cover. The components can be obtained with low cost. Before starting this step, the temperature is measured on the polymer net by a thermometer for 5 minutes, as shown in Figure 3-3. Since vapor HF etching has a rapid etching rate between 35° C and 40° C, hence the most important experimental parameter is the temperature on the chip. However, the temperature on the chip increases with the time during etching, so the initial temperature of etching is set at 35° C by adjusting the distance between the bulb and the chip in the setup (Figure 3-3).
Step P: Assembly
Finally, the released device is pushed by a microprobe.
Table 3-1 Parameters of vapor HF release
Description Parameters
Initial temperature on the chip 35° C
Figure 3-2 Schematic of the vapor HF release setup.
Figure 3-3 Temperature measurement before vapor HF release
3-1-2 Device 2
The fabrication process of Device 2 is simpler because the SU-8 photoresist is not used compared to Device 1. The process parameters are the same as for Device 1. The illustration is shown in Figure 3-4. Since SU-8 is not used in Device 2, anchor definition and SU-8 coating processes are not needed (Step E, F, G, H, I, L in Device 1).
Light bulb
Vapor HF Cover
Aqueous HF
Silicon chip Net
Thermometer
Step A: RCA cleaning (Step A in Device 1)
Step B: Photolithography – Device layer definition (Mask1) (Step B in Device 1)
Step C: Inductively coupled plasma silicon etching – Silicon of device layer etching (Step C in Device 1)
Step D: Backside silicon oxide deposition (Step D in Device 1)
Step E: Photolithography process on backside silicon oxide (Mask 2) (Step J in Device 1)
Step F: Polysilicon reactive ion etching (Poly-Si RIE) – Backside oxide etching (Step K in Device 1)
Step G: Wafer dicing
(Step M in Device 1)
Step H: Backside inductively coupled plasma deep silicon etching (Step N in Device 1)
Step I: Device release (Step O in Device 1) Step J: Assembly
(Step P in Device 1)
Buried oxide
(a) Structure layer patterning and backside oxide deposition (Step A, Step B, Step C StepD)
(b) Backside oxide definition (Step E, Step F)
(c) Backside ICP etching and oxide release (Step H, Step I)
Figure 3-4 Fabrication process (Device 2).
SOI Substrate
Buried oxide PECVD Oxide
SOI Substrate
Buried oxide PECVD Oxide AZ4620 photoresist
(d) Microprobe assembly (Step J)
Figure 3-4 Fabrication process (Device 2) (continued).
3-2 Fabrication issues and solutions
Adhesion and stiction problems were encountered in our previous study [7].
Adhesion problems between SU-8 and silicon were solved by immersing the wafer in the buffered oxide etchant (BOE) for 5 seconds before SU-8 coating to remove the native oxide. However, vapor HF releasing still resulted in stiction. These fabrication problems and their solutions are presented in this section.
3-2-1 Structure patterning
The ICP process provides a vertical etching for the structure layer. However, Poly-RIE can also be used to etch the 5-µm-thick silicon. A test was performed by using poly-RIE. Because the FH6400 photoresist was not thick enough as the etching mask for Poly-RIE, AZ4620 photoresist was used. In order to etch the 5-µm-thick silicon device layer, 5-µm-thick AZ4620 photoresist was needed with the etching selectivity of 1:1. Nevertheless, the shape of the AZ4620 photoresist would change after the long baking, as illustrated in Figure 3-5. As the structure layer, the vertical
Mirror Locking latch
Buried oxide
side wall is very important for it will affect the angular accuracy after the structure is lifted up. The test showed that ICP is still a better solution for the structure patterning.
Figure 3-5 (a) Illustration of AZ4620 photoresist as the etching mask, (b) before baking, (c) after baking.
3-2-2 Oxide etching
In step I, the oxide was first etched by Poly-RIE in Device 1. However, it was difficult to control the etching parameters to obtain uniform etching across the entire wafer by Poly-RIE. The residual oxide will result in problems with SU-8 adhesion.
Therefore, Poly-RIE was replaced by HDP-RIE, which has a better selectivity between oxide and silicon. Over etching was used to ensure complete removal of the oxide without etching the silicon device layer too much. In other words, process control could be improved by using HDP-RIE.
3-2-3 Vapor HF release
The most important step of the fabrication process is the release of the structure.
Vapor HF is a common solution to reduce possibility of stiction. The most important parameter in this step is the temperature of the chip. Due to the variation of the
process was needed. Temperature over 35° C would not result in stiction. Temperature under 40° C would result in water stains on the chip, as Figure 3-6 shows.
Temperature over 40° C would not result in any water stains but the etching rate was slow. Fortunately, the stains could be eliminated by baking for 5 minutes. Observation shows that the stains were much more easily produced in PECVD oxide etch than the buried oxide. Another notice is that the temperature of the chip was unstable at the beginning of the etch and the ambient mist would result in stiction. So the release process was divided into two steps and the parameters are shown in the following table. In Table 3-2, Step 2 was used for etching PECVD oxide and Step 5 was used for etching buried oxide. The baking in Step 3 to remove water stains from PECVD oxide etch could increase the etching rate in Step 5. The increased release time for the buried oxide etch could ensure complete removal of the sacrificial oxide in the structure. The temperature would increase continuously during the release process due to the heating by the light bulb before equilibrium was reached. The measured temperature was about 40° C after one hour. The increased release time would not damage the structure.
Table 3-2 Modified parameters of vapor HF release
Step Description Parameters
1 Temperature measurement 10 min (37° C ~40° C)
2 Release 40 minutes (PECVD oxide etching)
3 Hotplate baking 200° C, 5 min
4 Temperature measurement 10 min (37° C ~40° C)
5 Release 90 minutes (buried oxide etching)
6 Hotplate baking 200° C, 5 min
Figure 3-6 (a) Water stains on the chip after vapor HF etching, (b) after baking.
(a) (b)
3-3 Summary
The fabrication processes and problems were presented. The parameters of vapor HF release were tuned to the best condition to avoid the problem of stiction. The ratio of stiction decreased from 40% to 5%. Some SEM photographs of the fabricated structures are showed in Figure 3-7. In the next chapter, the assembly procedure and assembled devices will be presented.
(a) (b)
(c) (d)
Figure 3-7 Fabricated devices, (a) 90° device without side latch, (b) close-up view of the V-shaped hinge, (c) corner cube reflectors, (d) 45° device.